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617 lines
16 KiB
Diff
617 lines
16 KiB
Diff
From 3302e1e1a3cfa4e67fda2a61d6f0c42205d40932 Mon Sep 17 00:00:00 2001
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From: Rajith Cherian <rajith@codeaurora.org>
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Date: Tue, 14 Feb 2017 18:30:43 +0530
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Subject: [PATCH] ipq8064: tsens: Base tsens driver for IPQ8064
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Add TSENS driver template to support IPQ8064.
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This is a base file copied from tsens-8960.c
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Change-Id: I47c573fdfa2d898243c6a6ba952d1632f91391f7
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Signed-off-by: Rajith Cherian <rajith@codeaurora.org>
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ipq8064: tsens: TSENS driver support for IPQ8064
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Support for IPQ8064 tsens driver. The driver works
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with the thermal framework. The driver overrides the
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following fucntionalities:
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1. Get current temperature.
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2. Get/Set trip temperatures.
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3. Enabled/Disable trip points.
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4. ISR for threshold generated interrupt.
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5. Notify userspace when trip points are hit.
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Change-Id: I8bc7204fd627d10875ab13fc1de8cb6c2ed7a918
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Signed-off-by: Rajith Cherian <rajith@codeaurora.org>
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---
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--- a/drivers/thermal/qcom/Makefile
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+++ b/drivers/thermal/qcom/Makefile
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@@ -2,5 +2,5 @@
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obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o
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qcom_tsens-y += tsens.o tsens-common.o tsens-v0_1.o \
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- tsens-8960.o tsens-v2.o tsens-v1.o
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+ tsens-8960.o tsens-v2.o tsens-v1.o tsens-ipq8064.o
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obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o
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--- /dev/null
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+++ b/drivers/thermal/qcom/tsens-ipq8064.c
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@@ -0,0 +1,551 @@
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+/*
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+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 and
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+ * only version 2 as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ */
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+
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+#include <linux/platform_device.h>
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+#include <linux/delay.h>
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+#include <linux/bitops.h>
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+#include <linux/regmap.h>
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+#include <linux/thermal.h>
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+#include <linux/nvmem-consumer.h>
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+#include <linux/io.h>
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+#include <linux/interrupt.h>
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+#include "tsens.h"
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+
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+#define CAL_MDEGC 30000
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+
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+#define CONFIG_ADDR 0x3640
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+/* CONFIG_ADDR bitmasks */
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+#define CONFIG 0x9b
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+#define CONFIG_MASK 0xf
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+#define CONFIG_SHIFT 0
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+
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+#define STATUS_CNTL_8064 0x3660
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+#define CNTL_ADDR 0x3620
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+/* CNTL_ADDR bitmasks */
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+#define EN BIT(0)
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+#define SW_RST BIT(1)
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+#define SENSOR0_EN BIT(3)
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+#define SLP_CLK_ENA BIT(26)
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+#define MEASURE_PERIOD 1
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+#define SENSOR0_SHIFT 3
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+
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+/* INT_STATUS_ADDR bitmasks */
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+#define MIN_STATUS_MASK BIT(0)
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+#define LOWER_STATUS_CLR BIT(1)
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+#define UPPER_STATUS_CLR BIT(2)
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+#define MAX_STATUS_MASK BIT(3)
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+
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+#define THRESHOLD_ADDR 0x3624
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+/* THRESHOLD_ADDR bitmasks */
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+#define THRESHOLD_MAX_CODE 0x20000
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+#define THRESHOLD_MIN_CODE 0
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+#define THRESHOLD_MAX_LIMIT_SHIFT 24
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+#define THRESHOLD_MIN_LIMIT_SHIFT 16
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+#define THRESHOLD_UPPER_LIMIT_SHIFT 8
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+#define THRESHOLD_LOWER_LIMIT_SHIFT 0
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+#define THRESHOLD_MAX_LIMIT_MASK (THRESHOLD_MAX_CODE << \
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+ THRESHOLD_MAX_LIMIT_SHIFT)
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+#define THRESHOLD_MIN_LIMIT_MASK (THRESHOLD_MAX_CODE << \
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+ THRESHOLD_MIN_LIMIT_SHIFT)
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+#define THRESHOLD_UPPER_LIMIT_MASK (THRESHOLD_MAX_CODE << \
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+ THRESHOLD_UPPER_LIMIT_SHIFT)
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+#define THRESHOLD_LOWER_LIMIT_MASK (THRESHOLD_MAX_CODE << \
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+ THRESHOLD_LOWER_LIMIT_SHIFT)
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+
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+/* Initial temperature threshold values */
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+#define LOWER_LIMIT_TH 0x9d /* 95C */
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+#define UPPER_LIMIT_TH 0xa6 /* 105C */
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+#define MIN_LIMIT_TH 0x0
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+#define MAX_LIMIT_TH 0xff
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+
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+#define S0_STATUS_ADDR 0x3628
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+#define STATUS_ADDR_OFFSET 2
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+#define SENSOR_STATUS_SIZE 4
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+#define INT_STATUS_ADDR 0x363c
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+#define TRDY_MASK BIT(7)
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+#define TIMEOUT_US 100
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+
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+#define TSENS_EN BIT(0)
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+#define TSENS_SW_RST BIT(1)
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+#define TSENS_ADC_CLK_SEL BIT(2)
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+#define SENSOR0_EN BIT(3)
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+#define SENSOR1_EN BIT(4)
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+#define SENSOR2_EN BIT(5)
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+#define SENSOR3_EN BIT(6)
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+#define SENSOR4_EN BIT(7)
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+#define SENSORS_EN (SENSOR0_EN | SENSOR1_EN | \
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+ SENSOR2_EN | SENSOR3_EN | SENSOR4_EN)
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+#define TSENS_8064_SENSOR5_EN BIT(8)
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+#define TSENS_8064_SENSOR6_EN BIT(9)
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+#define TSENS_8064_SENSOR7_EN BIT(10)
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+#define TSENS_8064_SENSOR8_EN BIT(11)
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+#define TSENS_8064_SENSOR9_EN BIT(12)
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+#define TSENS_8064_SENSOR10_EN BIT(13)
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+#define TSENS_8064_SENSORS_EN (SENSORS_EN | \
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+ TSENS_8064_SENSOR5_EN | \
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+ TSENS_8064_SENSOR6_EN | \
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+ TSENS_8064_SENSOR7_EN | \
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+ TSENS_8064_SENSOR8_EN | \
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+ TSENS_8064_SENSOR9_EN | \
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+ TSENS_8064_SENSOR10_EN)
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+
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+#define TSENS_8064_SEQ_SENSORS 5
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+#define TSENS_8064_S4_S5_OFFSET 40
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+#define TSENS_FACTOR 1
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+
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+/* Trips: from very hot to very cold */
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+enum tsens_trip_type {
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+ TSENS_TRIP_STAGE3 = 0,
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+ TSENS_TRIP_STAGE2,
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+ TSENS_TRIP_STAGE1,
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+ TSENS_TRIP_STAGE0,
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+ TSENS_TRIP_NUM,
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+};
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+
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+u32 tsens_8064_slope[] = {
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+ 1176, 1176, 1154, 1176,
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+ 1111, 1132, 1132, 1199,
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+ 1132, 1199, 1132
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+ };
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+
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+/* Temperature on y axis and ADC-code on x-axis */
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+static inline int code_to_degC(u32 adc_code, const struct tsens_sensor *s)
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+{
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+ int degcbeforefactor, degc;
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+
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+ degcbeforefactor = (adc_code * s->slope) + s->offset;
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+
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+ if (degcbeforefactor == 0)
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+ degc = degcbeforefactor;
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+ else if (degcbeforefactor > 0)
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+ degc = (degcbeforefactor + TSENS_FACTOR/2)
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+ / TSENS_FACTOR;
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+ else
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+ degc = (degcbeforefactor - TSENS_FACTOR/2)
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+ / TSENS_FACTOR;
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+
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+ return degc;
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+}
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+
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+static int degC_to_code(int degC, const struct tsens_sensor *s)
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+{
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+ int code = ((degC * TSENS_FACTOR - s->offset) + (s->slope/2))
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+ / s->slope;
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+
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+ if (code > THRESHOLD_MAX_CODE)
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+ code = THRESHOLD_MAX_CODE;
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+ else if (code < THRESHOLD_MIN_CODE)
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+ code = THRESHOLD_MIN_CODE;
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+ return code;
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+}
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+
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+static int suspend_ipq8064(struct tsens_priv *priv)
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+{
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+ int ret;
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+ unsigned int mask;
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+ struct regmap *map = priv->tm_map;
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+
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+ ret = regmap_read(map, THRESHOLD_ADDR, &priv->ctx.threshold);
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+ if (ret)
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+ return ret;
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+
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+ ret = regmap_read(map, CNTL_ADDR, &priv->ctx.control);
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+ if (ret)
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+ return ret;
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+
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+ mask = SLP_CLK_ENA | EN;
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+
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+ ret = regmap_update_bits(map, CNTL_ADDR, mask, 0);
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+ if (ret)
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+ return ret;
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+
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+ return 0;
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+}
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+
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+static int resume_ipq8064(struct tsens_priv *priv)
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+{
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+ int ret;
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+ struct regmap *map = priv->tm_map;
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+
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+ ret = regmap_update_bits(map, CNTL_ADDR, SW_RST, SW_RST);
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+ if (ret)
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+ return ret;
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+
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+ ret = regmap_update_bits(map, CONFIG_ADDR, CONFIG_MASK, CONFIG);
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+ if (ret)
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+ return ret;
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+
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+ ret = regmap_write(map, THRESHOLD_ADDR, priv->ctx.threshold);
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+ if (ret)
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+ return ret;
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+
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+ ret = regmap_write(map, CNTL_ADDR, priv->ctx.control);
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+ if (ret)
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+ return ret;
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+
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+ return 0;
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+}
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+
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+static void notify_uspace_tsens_fn(struct work_struct *work)
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+{
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+ struct tsens_sensor *s = container_of(work, struct tsens_sensor,
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+ notify_work);
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+
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+ sysfs_notify(&s->tzd->device.kobj, NULL, "type");
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+}
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+
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+static void tsens_scheduler_fn(struct work_struct *work)
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+{
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+ struct tsens_priv *priv = container_of(work, struct tsens_priv,
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+ tsens_work);
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+ unsigned int threshold, threshold_low, code, reg, sensor, mask;
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+ unsigned int sensor_addr;
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+ bool upper_th_x, lower_th_x;
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+ int adc_code, ret;
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+
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+ ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, ®);
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+ if (ret)
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+ return;
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+ reg = reg | LOWER_STATUS_CLR | UPPER_STATUS_CLR;
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+ ret = regmap_write(priv->tm_map, STATUS_CNTL_8064, reg);
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+ if (ret)
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+ return;
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+
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+ mask = ~(LOWER_STATUS_CLR | UPPER_STATUS_CLR);
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+ ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, &threshold);
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+ if (ret)
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+ return;
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+ threshold_low = (threshold & THRESHOLD_LOWER_LIMIT_MASK)
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+ >> THRESHOLD_LOWER_LIMIT_SHIFT;
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+ threshold = (threshold & THRESHOLD_UPPER_LIMIT_MASK)
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+ >> THRESHOLD_UPPER_LIMIT_SHIFT;
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+
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+ ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, ®);
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+ if (ret)
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+ return;
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+
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+ ret = regmap_read(priv->tm_map, CNTL_ADDR, &sensor);
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+ if (ret)
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+ return;
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+ sensor &= (uint32_t) TSENS_8064_SENSORS_EN;
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+ sensor >>= SENSOR0_SHIFT;
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+
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+ /* Constraint: There is only 1 interrupt control register for all
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+ * 11 temperature sensor. So monitoring more than 1 sensor based
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+ * on interrupts will yield inconsistent result. To overcome this
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+ * issue we will monitor only sensor 0 which is the master sensor.
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+ */
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+
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+ /* Skip if the sensor is disabled */
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+ if (sensor & 1) {
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+ ret = regmap_read(priv->tm_map, priv->sensor[0].status, &code);
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+ if (ret)
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+ return;
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+ upper_th_x = code >= threshold;
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+ lower_th_x = code <= threshold_low;
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+ if (upper_th_x)
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+ mask |= UPPER_STATUS_CLR;
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+ if (lower_th_x)
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+ mask |= LOWER_STATUS_CLR;
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+ if (upper_th_x || lower_th_x) {
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+ /* Notify user space */
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+ schedule_work(&priv->sensor[0].notify_work);
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+ regmap_read(priv->tm_map, sensor_addr, &adc_code);
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+ pr_debug("Trigger (%d degrees) for sensor %d\n",
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+ code_to_degC(adc_code, &priv->sensor[0]), 0);
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+ }
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+ }
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+ regmap_write(priv->tm_map, STATUS_CNTL_8064, reg & mask);
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+
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+ /* force memory to sync */
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+ mb();
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+}
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+
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+static irqreturn_t tsens_isr(int irq, void *data)
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+{
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+ struct tsens_priv *priv = data;
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+
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+ schedule_work(&priv->tsens_work);
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+ return IRQ_HANDLED;
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+}
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+
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+static void hw_init(struct tsens_priv *priv)
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+{
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+ int ret;
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+ unsigned int reg_cntl = 0, reg_cfg = 0, reg_thr = 0;
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+ unsigned int reg_status_cntl = 0;
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+
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+ regmap_read(priv->tm_map, CNTL_ADDR, ®_cntl);
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+ regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl | TSENS_SW_RST);
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+
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+ reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18)
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+ | (((1 << priv->num_sensors) - 1) << SENSOR0_SHIFT);
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+ regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
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+ regmap_read(priv->tm_map, STATUS_CNTL_8064, ®_status_cntl);
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+ reg_status_cntl |= LOWER_STATUS_CLR | UPPER_STATUS_CLR
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+ | MIN_STATUS_MASK | MAX_STATUS_MASK;
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+ regmap_write(priv->tm_map, STATUS_CNTL_8064, reg_status_cntl);
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+ reg_cntl |= TSENS_EN;
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+ regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
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+
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+ regmap_read(priv->tm_map, CONFIG_ADDR, ®_cfg);
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+ reg_cfg = (reg_cfg & ~CONFIG_MASK) | (CONFIG << CONFIG_SHIFT);
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+ regmap_write(priv->tm_map, CONFIG_ADDR, reg_cfg);
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+
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+ reg_thr |= (LOWER_LIMIT_TH << THRESHOLD_LOWER_LIMIT_SHIFT)
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+ | (UPPER_LIMIT_TH << THRESHOLD_UPPER_LIMIT_SHIFT)
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+ | (MIN_LIMIT_TH << THRESHOLD_MIN_LIMIT_SHIFT)
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+ | (MAX_LIMIT_TH << THRESHOLD_MAX_LIMIT_SHIFT);
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+
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+ regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_thr);
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+
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+ ret = devm_request_irq(priv->dev, priv->tsens_irq, tsens_isr,
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+ IRQF_TRIGGER_RISING, "tsens_interrupt", priv);
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+ if (ret < 0) {
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+ pr_err("%s: request_irq FAIL: %d\n", __func__, ret);
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+ return;
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+ }
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+
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+ INIT_WORK(&priv->tsens_work, tsens_scheduler_fn);
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+}
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+
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+static int init_ipq8064(struct tsens_priv *priv)
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+{
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+ int ret, i;
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+ u32 reg_cntl, offset = 0;
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+
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+ init_common(priv);
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+ if (!priv->tm_map)
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+ return -ENODEV;
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+
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+ /*
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+ * The status registers for each sensor are discontiguous
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+ * because some SoCs have 5 sensors while others have more
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+ * but the control registers stay in the same place, i.e
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+ * directly after the first 5 status registers.
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+ */
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+ for (i = 0; i < priv->num_sensors; i++) {
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+ if (i >= TSENS_8064_SEQ_SENSORS)
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+ offset = TSENS_8064_S4_S5_OFFSET;
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+
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+ priv->sensor[i].status = S0_STATUS_ADDR + offset
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+ + (i << STATUS_ADDR_OFFSET);
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+ priv->sensor[i].slope = tsens_8064_slope[i];
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+ INIT_WORK(&priv->sensor[i].notify_work,
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+ notify_uspace_tsens_fn);
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+ }
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+
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+ reg_cntl = SW_RST;
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+ ret = regmap_update_bits(priv->tm_map, CNTL_ADDR, SW_RST, reg_cntl);
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+ if (ret)
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+ return ret;
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+
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+ reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18);
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+ reg_cntl &= ~SW_RST;
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+ ret = regmap_update_bits(priv->tm_map, CONFIG_ADDR,
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+ CONFIG_MASK, CONFIG);
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+
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+ reg_cntl |= GENMASK(priv->num_sensors - 1, 0) << SENSOR0_SHIFT;
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+ ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
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+ if (ret)
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+ return ret;
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+
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+ reg_cntl |= EN;
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+ ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
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+ if (ret)
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+ return ret;
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+
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+ return 0;
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+}
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+
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+static int calibrate_ipq8064(struct tsens_priv *priv)
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+{
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+ int i;
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+ char *data, *data_backup;
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+
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+ ssize_t num_read = priv->num_sensors;
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+ struct tsens_sensor *s = priv->sensor;
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+
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+ data = qfprom_read(priv->dev, "calib");
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+ if (IS_ERR(data)) {
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+ pr_err("Calibration not found.\n");
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+ return PTR_ERR(data);
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+ }
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+
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+ data_backup = qfprom_read(priv->dev, "calib_backup");
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+ if (IS_ERR(data_backup)) {
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+ pr_err("Backup calibration not found.\n");
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+ return PTR_ERR(data_backup);
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+ }
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+
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+ for (i = 0; i < num_read; i++) {
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+ s[i].calib_data = readb_relaxed(data + i);
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+ s[i].calib_data_backup = readb_relaxed(data_backup + i);
|
|
+
|
|
+ if (s[i].calib_data_backup)
|
|
+ s[i].calib_data = s[i].calib_data_backup;
|
|
+ if (!s[i].calib_data) {
|
|
+ pr_err("QFPROM TSENS calibration data not present\n");
|
|
+ return -ENODEV;
|
|
+ }
|
|
+ s[i].slope = tsens_8064_slope[i];
|
|
+ s[i].offset = CAL_MDEGC - (s[i].calib_data * s[i].slope);
|
|
+ }
|
|
+
|
|
+ hw_init(priv);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int get_temp_ipq8064(struct tsens_priv *priv, int id, int *temp)
|
|
+{
|
|
+ int ret;
|
|
+ u32 code, trdy;
|
|
+ const struct tsens_sensor *s = &priv->sensor[id];
|
|
+ unsigned long timeout;
|
|
+
|
|
+ timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
|
|
+ do {
|
|
+ ret = regmap_read(priv->tm_map, INT_STATUS_ADDR, &trdy);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+ if (!(trdy & TRDY_MASK))
|
|
+ continue;
|
|
+ ret = regmap_read(priv->tm_map, s->status, &code);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+ *temp = code_to_degC(code, s);
|
|
+ return 0;
|
|
+ } while (time_before(jiffies, timeout));
|
|
+
|
|
+ return -ETIMEDOUT;
|
|
+}
|
|
+
|
|
+static int set_trip_temp_ipq8064(void *data, int trip, int temp)
|
|
+{
|
|
+ unsigned int reg_th, reg_cntl;
|
|
+ int ret, code, code_chk, hi_code, lo_code;
|
|
+ const struct tsens_sensor *s = data;
|
|
+ struct tsens_priv *priv = s->priv;
|
|
+
|
|
+ code_chk = code = degC_to_code(temp, s);
|
|
+
|
|
+ if (code < THRESHOLD_MIN_CODE || code > THRESHOLD_MAX_CODE)
|
|
+ return -EINVAL;
|
|
+
|
|
+ ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, ®_cntl);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, ®_th);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ hi_code = (reg_th & THRESHOLD_UPPER_LIMIT_MASK)
|
|
+ >> THRESHOLD_UPPER_LIMIT_SHIFT;
|
|
+ lo_code = (reg_th & THRESHOLD_LOWER_LIMIT_MASK)
|
|
+ >> THRESHOLD_LOWER_LIMIT_SHIFT;
|
|
+
|
|
+ switch (trip) {
|
|
+ case TSENS_TRIP_STAGE3:
|
|
+ code <<= THRESHOLD_MAX_LIMIT_SHIFT;
|
|
+ reg_th &= ~THRESHOLD_MAX_LIMIT_MASK;
|
|
+ break;
|
|
+ case TSENS_TRIP_STAGE2:
|
|
+ if (code_chk <= lo_code)
|
|
+ return -EINVAL;
|
|
+ code <<= THRESHOLD_UPPER_LIMIT_SHIFT;
|
|
+ reg_th &= ~THRESHOLD_UPPER_LIMIT_MASK;
|
|
+ break;
|
|
+ case TSENS_TRIP_STAGE1:
|
|
+ if (code_chk >= hi_code)
|
|
+ return -EINVAL;
|
|
+ code <<= THRESHOLD_LOWER_LIMIT_SHIFT;
|
|
+ reg_th &= ~THRESHOLD_LOWER_LIMIT_MASK;
|
|
+ break;
|
|
+ case TSENS_TRIP_STAGE0:
|
|
+ code <<= THRESHOLD_MIN_LIMIT_SHIFT;
|
|
+ reg_th &= ~THRESHOLD_MIN_LIMIT_MASK;
|
|
+ break;
|
|
+ default:
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ ret = regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_th | code);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int set_trip_activate_ipq8064(void *data, int trip,
|
|
+ enum thermal_trip_activation_mode mode)
|
|
+{
|
|
+ unsigned int reg_cntl, mask, val;
|
|
+ const struct tsens_sensor *s = data;
|
|
+ struct tsens_priv *priv = s->priv;
|
|
+ int ret;
|
|
+
|
|
+ if (!priv || trip < 0)
|
|
+ return -EINVAL;
|
|
+
|
|
+ ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, ®_cntl);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ switch (trip) {
|
|
+ case TSENS_TRIP_STAGE3:
|
|
+ mask = MAX_STATUS_MASK;
|
|
+ break;
|
|
+ case TSENS_TRIP_STAGE2:
|
|
+ mask = UPPER_STATUS_CLR;
|
|
+ break;
|
|
+ case TSENS_TRIP_STAGE1:
|
|
+ mask = LOWER_STATUS_CLR;
|
|
+ break;
|
|
+ case TSENS_TRIP_STAGE0:
|
|
+ mask = MIN_STATUS_MASK;
|
|
+ break;
|
|
+ default:
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ if (mode == THERMAL_TRIP_ACTIVATION_DISABLED)
|
|
+ val = reg_cntl | mask;
|
|
+ else
|
|
+ val = reg_cntl & ~mask;
|
|
+
|
|
+ ret = regmap_write(priv->tm_map, STATUS_CNTL_8064, val);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ /* force memory to sync */
|
|
+ mb();
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+const struct tsens_ops ops_ipq8064 = {
|
|
+ .init = init_ipq8064,
|
|
+ .calibrate = calibrate_ipq8064,
|
|
+ .get_temp = get_temp_ipq8064,
|
|
+ .suspend = suspend_ipq8064,
|
|
+ .resume = resume_ipq8064,
|
|
+ .set_trip_temp = set_trip_temp_ipq8064,
|
|
+ .set_trip_activate = set_trip_activate_ipq8064,
|
|
+};
|
|
+
|
|
+const struct tsens_plat_data data_ipq8064 = {
|
|
+ .num_sensors = 11,
|
|
+ .ops = &ops_ipq8064,
|
|
+};
|
|
--- a/drivers/thermal/qcom/tsens.c
|
|
+++ b/drivers/thermal/qcom/tsens.c
|
|
@@ -69,8 +69,11 @@ static const struct of_device_id tsens_t
|
|
}, {
|
|
.compatible = "qcom,tsens-v2",
|
|
.data = &data_tsens_v2,
|
|
+ }, {
|
|
+ .compatible = "qcom,ipq8064-tsens",
|
|
+ .data = &data_ipq8064,
|
|
},
|
|
- {}
|
|
+ {}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, tsens_table);
|
|
|
|
--- a/drivers/thermal/qcom/tsens.h
|
|
+++ b/drivers/thermal/qcom/tsens.h
|
|
@@ -324,7 +324,7 @@ extern const struct tsens_plat_data data
|
|
extern const struct tsens_plat_data data_8916, data_8974;
|
|
|
|
/* TSENS v1 targets */
|
|
-extern const struct tsens_plat_data data_tsens_v1;
|
|
+extern const struct tsens_plat_data data_tsens_v1, data_ipq8064;
|
|
|
|
/* TSENS v2 targets */
|
|
extern const struct tsens_plat_data data_8996, data_tsens_v2;
|