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351 lines
10 KiB
Diff
351 lines
10 KiB
Diff
Subject: [PATCH v12 14/14] cpufreq: qcom: Add support for krait based socs
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Date: Tue, 14 Aug 2018 17:42:33 +0530
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Message-Id: <1534248753-2440-15-git-send-email-sricharan@codeaurora.org>
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X-Mailer: git-send-email 1.9.1
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In-Reply-To: <1534248753-2440-1-git-send-email-sricharan@codeaurora.org>
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References: <1534248753-2440-1-git-send-email-sricharan@codeaurora.org>
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Sender: linux-kernel-owner@vger.kernel.org
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Precedence: bulk
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List-ID: <linux-kernel.vger.kernel.org>
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X-Mailing-List: linux-kernel@vger.kernel.org
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In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
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that has KRAIT processors the voltage/current value of each OPP
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varies based on the silicon variant in use.
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The required OPP related data is determined based on
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the efuse value. This is similar to the existing code for
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kryo cores. So adding support for krait cores here.
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Signed-off-by: Sricharan R <sricharan@codeaurora.org>
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---
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.../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 3 +-
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drivers/cpufreq/Kconfig.arm | 2 +-
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drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
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drivers/cpufreq/qcom-cpufreq-nvmem.c | 151 +++++++++++++++++++--
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4 files changed, 149 insertions(+), 12 deletions(-)
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# diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
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# index 6dcdfcd..7bc0f1a 100644
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# --- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
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# +++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
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# @@ -19,7 +19,8 @@ In 'cpus' nodes:
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# In 'operating-points-v2' table:
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# - compatible: Should be
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# - - 'operating-points-v2-qcom-cpu' for apq8096 and msm8996.
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# + - 'operating-points-v2-qcom-cpu' for apq8096, msm8996, msm8974,
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# + apq8064, msm8960 and ipq8074.
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# - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
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# efuse registers that has information about the
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# speedbin that is used to select the right frequency/voltage
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--- a/drivers/cpufreq/Kconfig.arm
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+++ b/drivers/cpufreq/Kconfig.arm
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@@ -134,7 +134,7 @@ config ARM_OMAP2PLUS_CPUFREQ
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config ARM_QCOM_CPUFREQ_NVMEM
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tristate "Qualcomm nvmem based CPUFreq"
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- depends on ARM64
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+ depends on ARCH_QCOM
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depends on QCOM_QFPROM
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depends on QCOM_SMEM
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select PM_OPP
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--- a/drivers/cpufreq/cpufreq-dt-platdev.c
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+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
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@@ -138,6 +138,11 @@ static const struct of_device_id blackli
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{ .compatible = "ti,am43", },
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{ .compatible = "ti,dra7", },
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+ { .compatible = "qcom,ipq8064", },
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+ { .compatible = "qcom,apq8064", },
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+ { .compatible = "qcom,msm8974", },
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+ { .compatible = "qcom,msm8960", },
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+
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{ }
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};
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--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
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+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
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@@ -49,12 +49,14 @@ struct qcom_cpufreq_drv;
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struct qcom_cpufreq_match_data {
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int (*get_version)(struct device *cpu_dev,
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struct nvmem_cell *speedbin_nvmem,
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+ char **pvs_name,
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struct qcom_cpufreq_drv *drv);
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const char **genpd_names;
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};
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struct qcom_cpufreq_drv {
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- struct opp_table **opp_tables;
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+ struct opp_table **opp_tables1;
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+ struct opp_table **opp_tables2;
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struct opp_table **genpd_opp_tables;
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u32 versions;
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const struct qcom_cpufreq_match_data *data;
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@@ -62,6 +64,79 @@ struct qcom_cpufreq_drv {
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static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
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+static void get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver,
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+ struct nvmem_cell *pvs_nvmem, u8 *buf)
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+{
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+ u32 pte_efuse;
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+
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+ pte_efuse = *((u32 *)buf);
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+
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+ *speed = pte_efuse & 0xf;
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+ if (*speed == 0xf)
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+ *speed = (pte_efuse >> 4) & 0xf;
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+
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+ if (*speed == 0xf) {
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+ *speed = 0;
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+ pr_warn("Speed bin: Defaulting to %d\n", *speed);
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+ } else {
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+ pr_info("Speed bin: %d\n", *speed);
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+ }
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+
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+ *pvs = (pte_efuse >> 10) & 0x7;
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+ if (*pvs == 0x7)
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+ *pvs = (pte_efuse >> 13) & 0x7;
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+
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+ if (*pvs == 0x7) {
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+ *pvs = 0;
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+ pr_warn("PVS bin: Defaulting to %d\n", *pvs);
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+ } else {
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+ pr_info("PVS bin: %d\n", *pvs);
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+ }
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+}
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+
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+static void get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver,
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+ struct nvmem_cell *pvs_nvmem, u8 *buf)
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+{
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+ u32 pte_efuse, redundant_sel;
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+
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+ pte_efuse = *((u32 *)buf);
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+ redundant_sel = (pte_efuse >> 24) & 0x7;
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+ *speed = pte_efuse & 0x7;
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+
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+ /* 4 bits of PVS are in efuse register bits 31, 8-6. */
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+ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
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+ *pvs_ver = (pte_efuse >> 4) & 0x3;
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+
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+ switch (redundant_sel) {
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+ case 1:
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+ *speed = (pte_efuse >> 27) & 0xf;
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+ break;
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+ case 2:
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+ *pvs = (pte_efuse >> 27) & 0xf;
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+ break;
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+ }
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+
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+ /* Check SPEED_BIN_BLOW_STATUS */
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+ if (pte_efuse & BIT(3)) {
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+ pr_info("Speed bin: %d\n", *speed);
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+ } else {
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+ pr_warn("Speed bin not set. Defaulting to 0!\n");
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+ *speed = 0;
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+ }
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+
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+ /* Check PVS_BLOW_STATUS */
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+ pte_efuse = *(((u32 *)buf) + 4);
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+ pte_efuse &= BIT(21);
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+ if (pte_efuse) {
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+ pr_info("PVS bin: %d\n", *pvs);
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+ } else {
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+ pr_warn("PVS bin not set. Defaulting to 0!\n");
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+ *pvs = 0;
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+ }
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+
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+ pr_info("PVS version: %d\n", *pvs_ver);
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+}
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+
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static enum _msm8996_version qcom_cpufreq_get_msm_id(void)
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{
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size_t len;
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@@ -93,11 +168,13 @@ static enum _msm8996_version qcom_cpufre
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static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
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struct nvmem_cell *speedbin_nvmem,
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+ char **pvs_name,
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struct qcom_cpufreq_drv *drv)
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{
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size_t len;
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u8 *speedbin;
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enum _msm8996_version msm8996_version;
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+ *pvs_name = NULL;
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msm8996_version = qcom_cpufreq_get_msm_id();
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if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
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@@ -125,10 +202,44 @@ static int qcom_cpufreq_kryo_name_versio
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return 0;
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}
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+static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
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+ struct nvmem_cell *speedbin_nvmem,
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+ char **pvs_name,
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+ struct qcom_cpufreq_drv *drv)
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+{
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+ int speed = 0, pvs = 0, pvs_ver = 0;
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+ u8 *speedbin;
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+ size_t len;
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+
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+ speedbin = nvmem_cell_read(speedbin_nvmem, &len);
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+ if (len == 4) {
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+ get_krait_bin_format_a(&speed, &pvs, &pvs_ver,
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+ speedbin_nvmem, speedbin);
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+ } else if (len == 8) {
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+ get_krait_bin_format_b(&speed, &pvs, &pvs_ver,
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+ speedbin_nvmem, speedbin);
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+ } else {
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+ dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
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+ return -ENODEV;
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+ }
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+
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+ snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
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+ speed, pvs, pvs_ver);
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+
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+ drv->versions = (1 << speed);
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+
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+ kfree(speedbin);
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+ return 0;
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+}
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+
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static const struct qcom_cpufreq_match_data match_data_kryo = {
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.get_version = qcom_cpufreq_kryo_name_version,
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};
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+static const struct qcom_cpufreq_match_data match_data_krait = {
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+ .get_version = qcom_cpufreq_krait_name_version,
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+};
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+
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static const char *qcs404_genpd_names[] = { "cpr", NULL };
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static const struct qcom_cpufreq_match_data match_data_qcs404 = {
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@@ -141,6 +252,7 @@ static int qcom_cpufreq_probe(struct pla
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struct nvmem_cell *speedbin_nvmem;
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struct device_node *np;
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struct device *cpu_dev;
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+ char *pvs_name = "speedXX-pvsXX-vXX";
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unsigned cpu;
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const struct of_device_id *match;
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int ret;
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@@ -153,7 +265,7 @@ static int qcom_cpufreq_probe(struct pla
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if (!np)
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return -ENOENT;
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- ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
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+ ret = of_device_is_compatible(np, "operating-points-v2-qcom-cpu");
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if (!ret) {
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of_node_put(np);
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return -ENOENT;
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@@ -181,7 +293,7 @@ static int qcom_cpufreq_probe(struct pla
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goto free_drv;
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}
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- ret = drv->data->get_version(cpu_dev, speedbin_nvmem, drv);
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+ ret = drv->data->get_version(cpu_dev, speedbin_nvmem, &pvs_name, drv);
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if (ret) {
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nvmem_cell_put(speedbin_nvmem);
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goto free_drv;
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@@ -190,12 +302,18 @@ static int qcom_cpufreq_probe(struct pla
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}
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of_node_put(np);
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- drv->opp_tables = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables),
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+ drv->opp_tables1 = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables1),
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GFP_KERNEL);
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- if (!drv->opp_tables) {
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+ if (!drv->opp_tables1) {
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ret = -ENOMEM;
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goto free_drv;
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}
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+ drv->opp_tables2 = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables2),
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+ GFP_KERNEL);
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+ if (!drv->opp_tables2) {
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+ ret = -ENOMEM;
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+ goto free_opp1;
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+ }
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drv->genpd_opp_tables = kcalloc(num_possible_cpus(),
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sizeof(*drv->genpd_opp_tables),
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@@ -213,11 +331,22 @@ static int qcom_cpufreq_probe(struct pla
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}
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if (drv->data->get_version) {
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- drv->opp_tables[cpu] =
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- dev_pm_opp_set_supported_hw(cpu_dev,
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+
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+ if (pvs_name) {
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+ drv->opp_tables1[cpu] = dev_pm_opp_set_prop_name(cpu_dev,
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+ pvs_name);
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+ if (IS_ERR(drv->opp_tables1[cpu])) {
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+ ret = PTR_ERR(drv->opp_tables1[cpu]);
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+ dev_err(cpu_dev, "Failed to add OPP name %s\n",
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+ pvs_name);
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+ goto free_opp;
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+ }
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+ }
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+
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+ drv->opp_tables2[cpu] = dev_pm_opp_set_supported_hw(cpu_dev,
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&drv->versions, 1);
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- if (IS_ERR(drv->opp_tables[cpu])) {
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- ret = PTR_ERR(drv->opp_tables[cpu]);
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+ if (IS_ERR(drv->opp_tables2[cpu])) {
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+ ret = PTR_ERR(drv->opp_tables2[cpu]);
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dev_err(cpu_dev,
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"Failed to set supported hardware\n");
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goto free_genpd_opp;
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@@ -259,11 +388,18 @@ free_genpd_opp:
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kfree(drv->genpd_opp_tables);
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free_opp:
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for_each_possible_cpu(cpu) {
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- if (IS_ERR_OR_NULL(drv->opp_tables[cpu]))
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+ if (IS_ERR_OR_NULL(drv->opp_tables1[cpu]))
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+ break;
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+ dev_pm_opp_put_prop_name(drv->opp_tables1[cpu]);
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+ }
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+ for_each_possible_cpu(cpu) {
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+ if (IS_ERR_OR_NULL(drv->opp_tables2[cpu]))
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break;
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- dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]);
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+ dev_pm_opp_put_supported_hw(drv->opp_tables2[cpu]);
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}
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- kfree(drv->opp_tables);
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+ kfree(drv->opp_tables2);
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+free_opp1:
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+ kfree(drv->opp_tables1);
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free_drv:
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kfree(drv);
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@@ -278,13 +414,16 @@ static int qcom_cpufreq_remove(struct pl
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platform_device_unregister(cpufreq_dt_pdev);
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for_each_possible_cpu(cpu) {
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- if (drv->opp_tables[cpu])
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- dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]);
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+ if (drv->opp_tables1[cpu])
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+ dev_pm_opp_put_supported_hw(drv->opp_tables1[cpu]);
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+ if (drv->opp_tables2[cpu])
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+ dev_pm_opp_put_supported_hw(drv->opp_tables2[cpu]);
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if (drv->genpd_opp_tables[cpu])
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dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]);
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}
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- kfree(drv->opp_tables);
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+ kfree(drv->opp_tables1);
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+ kfree(drv->opp_tables2);
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kfree(drv->genpd_opp_tables);
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kfree(drv);
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@@ -303,6 +442,10 @@ static const struct of_device_id qcom_cp
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{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
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{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
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{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
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+ { .compatible = "qcom,ipq8064", .data = &match_data_krait },
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+ { .compatible = "qcom,apq8064", .data = &match_data_krait },
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+ { .compatible = "qcom,msm8974", .data = &match_data_krait },
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+ { .compatible = "qcom,msm8960", .data = &match_data_krait },
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{},
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};
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