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109 lines
3.7 KiB
Diff
109 lines
3.7 KiB
Diff
From 89556b1a4d98fbfe498c8f26e988cbb8266f7dfe Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sat, 27 Jun 2015 13:17:35 +0200
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Subject: [PATCH 67/76] arm: mediatek: add mt7623 support
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/arm/mach-mediatek/Kconfig | 6 ++
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arch/arm/mach-mediatek/mediatek.c | 2 +
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.../dt-bindings/reset-controller/mt7623-resets.h | 59 ++++++++++++++++++++
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3 files changed, 67 insertions(+)
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create mode 100644 include/dt-bindings/reset-controller/mt7623-resets.h
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--- a/arch/arm/mach-mediatek/Kconfig
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+++ b/arch/arm/mach-mediatek/Kconfig
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@@ -17,6 +17,12 @@ config MACH_MT6592
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bool "MediaTek MT6592 SoCs support"
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default ARCH_MEDIATEK
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+config MACH_MT7623
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+ bool "MediaTek MT7623 SoCs support"
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+ default ARCH_MEDIATEK
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+ select ARCH_HAS_PCI
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+ select PCI
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+
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config MACH_MT8127
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bool "MediaTek MT8127 SoCs support"
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default ARCH_MEDIATEK
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--- a/arch/arm/mach-mediatek/mediatek.c
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+++ b/arch/arm/mach-mediatek/mediatek.c
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@@ -29,6 +29,7 @@ static void __init mediatek_timer_init(v
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void __iomem *gpt_base = 0;
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if (of_machine_is_compatible("mediatek,mt6589") ||
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+ of_machine_is_compatible("mediatek,mt7623") ||
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of_machine_is_compatible("mediatek,mt8135") ||
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of_machine_is_compatible("mediatek,mt8127")) {
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/* turn on GPT6 which ungates arch timer clocks */
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@@ -48,6 +49,7 @@ static void __init mediatek_timer_init(v
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static const char * const mediatek_board_dt_compat[] = {
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"mediatek,mt6589",
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"mediatek,mt6592",
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+ "mediatek,mt7623",
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"mediatek,mt8127",
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"mediatek,mt8135",
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NULL,
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--- /dev/null
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+++ b/include/dt-bindings/reset-controller/mt7623-resets.h
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@@ -0,0 +1,59 @@
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+/*
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+ * Copyright (c) 2015 OpenWrt
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+ * Author: John Crispin
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7623
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+#define _DT_BINDINGS_RESET_CONTROLLER_MT7623
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+
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+/* INFRACFG resets */
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+#define MT7623_INFRA_EMI_REG_RST 0
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+#define MT7623_INFRA_DRAMC0_A0_RST 1
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+#define MT7623_INFRA_FHCTL_RST 2
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+#define MT7623_INFRA_APCIRQ_EINT_RST 3
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+#define MT7623_INFRA_APXGPT_RST 4
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+#define MT7623_INFRA_SCPSYS_RST 5
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+#define MT7623_INFRA_KP_RST 6
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+#define MT7623_INFRA_PMIC_WRAP_RST 7
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+#define MT7623_INFRA_MIPI_RST 8
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+#define MT7623_INFRA_IRRX_RST 9
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+#define MT7623_INFRA_CEC_RST 10
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+#define MT7623_INFRA_EMI_RST 32
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+#define MT7623_INFRA_DRAMC0_RST 34
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+#define MT7623_INFRA_SMI_RST 37
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+#define MT7623_INFRA_M4U_RST 38
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+
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+/* PERICFG resets */
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+#define MT7623_PERI_UART0_SW_RST 0
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+#define MT7623_PERI_UART1_SW_RST 1
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+#define MT7623_PERI_UART2_SW_RST 2
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+#define MT7623_PERI_UART3_SW_RST 3
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+#define MT7623_PERI_GCPU_SW_RST 5
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+#define MT7623_PERI_BTIF_SW_RST 6
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+#define MT7623_PERI_PWM_SW_RST 8
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+#define MT7623_PERI_AUXADC_SW_RST 10
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+#define MT7623_PERI_DMA_SW_RST 11
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+#define MT7623_PERI_NFI_SW_RST 14
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+#define MT7623_PERI_NLI_SW_RST 15
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+#define MT7623_PERI_THERM_SW_RST 16
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+#define MT7623_PERI_MSDC0_SW_RST 17
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+#define MT7623_PERI_MSDC1_SW_RST 19
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+#define MT7623_PERI_MSDC2_SW_RST 20
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+#define MT7623_PERI_I2C0_SW_RST 22
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+#define MT7623_PERI_I2C1_SW_RST 23
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+#define MT7623_PERI_I2C2_SW_RST 24
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+#define MT7623_PERI_I2C3_SW_RST 25
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+#define MT7623_PERI_USB_SW_RST 28
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+#define MT7623_PERI_ETH_SW_RST 29
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+#define MT7623_PERI_SPI0_SW_RST 33
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+
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+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7623 */
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