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144 lines
4.2 KiB
Diff
144 lines
4.2 KiB
Diff
From 4751c1c74bc7b596db5de0c93be1a22a570145c0 Mon Sep 17 00:00:00 2001
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From: Ernst Schwab <eschwab@online.de>
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Date: Thu, 18 Feb 2010 12:47:46 +0100
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Subject: [PATCH] spi/mmc_spi: mmc_spi adaptations for SPI bus locking API
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Modification of the mmc_spi driver to use the SPI bus locking API.
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With this, the mmc_spi driver can be used together with other SPI
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devices on the same SPI bus. The exclusive access to the SPI bus is
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now managed in the SPI layer. The counting of chip selects in the probe
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function is no longer needed.
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Signed-off-by: Ernst Schwab <eschwab@online.de>
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Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Tested-by: Matt Fleming <matt@console-pimps.org>
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Tested-by: Antonio Ospite <ospite@studenti.unina.it>
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---
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drivers/mmc/host/mmc_spi.c | 59 ++++++++-----------------------------------
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1 files changed, 11 insertions(+), 48 deletions(-)
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--- a/drivers/mmc/host/mmc_spi.c
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+++ b/drivers/mmc/host/mmc_spi.c
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@@ -181,7 +181,7 @@ mmc_spi_readbytes(struct mmc_spi_host *h
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host->data_dma, sizeof(*host->data),
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DMA_FROM_DEVICE);
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- status = spi_sync(host->spi, &host->readback);
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+ status = spi_sync_locked(host->spi, &host->readback);
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if (host->dma_dev)
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dma_sync_single_for_cpu(host->dma_dev,
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@@ -540,7 +540,7 @@ mmc_spi_command_send(struct mmc_spi_host
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host->data_dma, sizeof(*host->data),
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DMA_BIDIRECTIONAL);
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}
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- status = spi_sync(host->spi, &host->m);
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+ status = spi_sync_locked(host->spi, &host->m);
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if (host->dma_dev)
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dma_sync_single_for_cpu(host->dma_dev,
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@@ -684,7 +684,7 @@ mmc_spi_writeblock(struct mmc_spi_host *
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host->data_dma, sizeof(*scratch),
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DMA_BIDIRECTIONAL);
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- status = spi_sync(spi, &host->m);
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+ status = spi_sync_locked(spi, &host->m);
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if (status != 0) {
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dev_dbg(&spi->dev, "write error (%d)\n", status);
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@@ -821,7 +821,7 @@ mmc_spi_readblock(struct mmc_spi_host *h
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DMA_FROM_DEVICE);
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}
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- status = spi_sync(spi, &host->m);
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+ status = spi_sync_locked(spi, &host->m);
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if (host->dma_dev) {
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dma_sync_single_for_cpu(host->dma_dev,
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@@ -1017,7 +1017,7 @@ mmc_spi_data_do(struct mmc_spi_host *hos
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host->data_dma, sizeof(*scratch),
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DMA_BIDIRECTIONAL);
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- tmp = spi_sync(spi, &host->m);
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+ tmp = spi_sync_locked(spi, &host->m);
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if (host->dma_dev)
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dma_sync_single_for_cpu(host->dma_dev,
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@@ -1083,6 +1083,9 @@ static void mmc_spi_request(struct mmc_h
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}
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#endif
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+ /* request exclusive bus access */
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+ spi_bus_lock(host->spi->master);
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+
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/* issue command; then optionally data and stop */
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status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL);
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if (status == 0 && mrq->data) {
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@@ -1093,6 +1096,9 @@ static void mmc_spi_request(struct mmc_h
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mmc_cs_off(host);
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}
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+ /* release the bus */
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+ spi_bus_unlock(host->spi->master);
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+
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mmc_request_done(host->mmc, mrq);
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}
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@@ -1289,23 +1295,6 @@ mmc_spi_detect_irq(int irq, void *mmc)
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return IRQ_HANDLED;
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}
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-struct count_children {
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- unsigned n;
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- struct bus_type *bus;
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-};
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-
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-static int maybe_count_child(struct device *dev, void *c)
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-{
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- struct count_children *ccp = c;
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-
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- if (dev->bus == ccp->bus) {
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- if (ccp->n)
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- return -EBUSY;
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- ccp->n++;
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- }
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- return 0;
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-}
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-
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static int mmc_spi_probe(struct spi_device *spi)
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{
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void *ones;
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@@ -1337,32 +1326,6 @@ static int mmc_spi_probe(struct spi_devi
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return status;
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}
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- /* We can use the bus safely iff nobody else will interfere with us.
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- * Most commands consist of one SPI message to issue a command, then
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- * several more to collect its response, then possibly more for data
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- * transfer. Clocking access to other devices during that period will
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- * corrupt the command execution.
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- *
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- * Until we have software primitives which guarantee non-interference,
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- * we'll aim for a hardware-level guarantee.
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- *
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- * REVISIT we can't guarantee another device won't be added later...
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- */
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- if (spi->master->num_chipselect > 1) {
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- struct count_children cc;
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-
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- cc.n = 0;
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- cc.bus = spi->dev.bus;
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- status = device_for_each_child(spi->dev.parent, &cc,
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- maybe_count_child);
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- if (status < 0) {
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- dev_err(&spi->dev, "can't share SPI bus\n");
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- return status;
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- }
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-
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- dev_warn(&spi->dev, "ASSUMING SPI bus stays unshared!\n");
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- }
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-
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/* We need a supply of ones to transmit. This is the only time
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* the CPU touches these, so cache coherency isn't a concern.
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*
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