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274 lines
6.9 KiB
Diff
274 lines
6.9 KiB
Diff
--- a/drivers/clk/clk-oxnas.c
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+++ b/drivers/clk/clk-oxnas.c
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@@ -16,19 +16,42 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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+#include <linux/clk.h>
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+#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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+#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/stringify.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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+#include <linux/reset.h>
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#include <dt-bindings/clock/oxsemi,ox810se.h>
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#include <dt-bindings/clock/oxsemi,ox820.h>
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+#define REF300_DIV_INT_SHIFT 8
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+#define REF300_DIV_FRAC_SHIFT 0
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+#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT)
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+#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT)
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+
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+#define PLLB_BYPASS 1
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+#define PLLB_ENSAT 3
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+#define PLLB_OUTDIV 4
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+#define PLLB_REFDIV 8
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+#define PLLB_DIV_INT_SHIFT 8
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+#define PLLB_DIV_FRAC_SHIFT 0
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+#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT)
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+#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT)
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+
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+#define PLLA_REFDIV_MASK 0x3F
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+#define PLLA_REFDIV_SHIFT 8
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+#define PLLA_OUTDIV_MASK 0x7
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+#define PLLA_OUTDIV_SHIFT 4
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+
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/* Standard regmap gate clocks */
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struct clk_oxnas_gate {
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struct clk_hw hw;
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@@ -49,6 +70,135 @@ struct oxnas_stdclk_data {
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#define CLK_SET_REGOFFSET 0x2c
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#define CLK_CLR_REGOFFSET 0x30
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+#define PLLA_CTRL0_REGOFFSET 0x1f0
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+#define PLLA_CTRL1_REGOFFSET 0x1f4
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+#define PLLB_CTRL0_REGOFFSET 0x1001f0
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+#define MHZ (1000 * 1000)
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+
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+struct clk_oxnas_pll {
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+ struct clk_hw hw;
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+ struct device_node *devnode;
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+ struct reset_control *rstc;
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+ struct regmap *syscon;
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+};
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+
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+#define to_clk_oxnas_pll(_hw) container_of(_hw, struct clk_oxnas_pll, hw)
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+
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+static unsigned long plla_clk_recalc_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ struct clk_oxnas_pll *plla = to_clk_oxnas_pll(hw);
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+ unsigned long fin = parent_rate;
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+ unsigned long refdiv, outdiv;
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+ unsigned int pll0, fbdiv;
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+
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+ BUG_ON(regmap_read(plla->syscon, PLLA_CTRL0_REGOFFSET, &pll0));
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+
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+ refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK;
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+ refdiv += 1;
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+ outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK;
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+ outdiv += 1;
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+
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+ BUG_ON(regmap_read(plla->syscon, PLLA_CTRL1_REGOFFSET, &fbdiv));
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+ /* seems we will not be here when pll is bypassed, so ignore this
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+ * case */
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+
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+ return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ;
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+}
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+
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+static const char *pll_clk_parents[] = {
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+ "oscillator",
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+};
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+
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+static struct clk_ops plla_ops = {
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+ .recalc_rate = plla_clk_recalc_rate,
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+};
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+
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+static struct clk_init_data clk_plla_init = {
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+ .name = "plla",
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+ .ops = &plla_ops,
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+ .parent_names = pll_clk_parents,
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+ .num_parents = ARRAY_SIZE(pll_clk_parents),
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+};
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+
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+static int pllb_clk_is_prepared(struct clk_hw *hw)
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+{
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+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
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+
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+ return !!pllb->rstc;
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+}
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+
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+static int pllb_clk_prepare(struct clk_hw *hw)
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+{
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+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
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+
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+ pllb->rstc = of_reset_control_get(pllb->devnode, NULL);
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+
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+ return IS_ERR(pllb->rstc) ? PTR_ERR(pllb->rstc) : 0;
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+}
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+
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+static void pllb_clk_unprepare(struct clk_hw *hw)
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+{
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+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
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+
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+ BUG_ON(IS_ERR(pllb->rstc));
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+
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+ reset_control_put(pllb->rstc);
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+ pllb->rstc = NULL;
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+}
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+
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+static int pllb_clk_enable(struct clk_hw *hw)
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+{
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+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
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+
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+ BUG_ON(IS_ERR(pllb->rstc));
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+
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+ /* put PLL into bypass */
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+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS));
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+ wmb();
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+ udelay(10);
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+ reset_control_assert(pllb->rstc);
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+ udelay(10);
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+ /* set PLL B control information */
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+ regmap_write_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, 0xffff,
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+ (1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV));
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+ reset_control_deassert(pllb->rstc);
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+ udelay(100);
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+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), 0);
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+
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+ return 0;
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+}
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+
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+static void pllb_clk_disable(struct clk_hw *hw)
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+{
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+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
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+
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+ BUG_ON(IS_ERR(pllb->rstc));
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+
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+ /* put PLL into bypass */
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+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS));
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+
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+ wmb();
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+ udelay(10);
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+
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+ reset_control_assert(pllb->rstc);
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+}
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+
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+static struct clk_ops pllb_ops = {
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+ .prepare = pllb_clk_prepare,
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+ .unprepare = pllb_clk_unprepare,
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+ .is_prepared = pllb_clk_is_prepared,
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+ .enable = pllb_clk_enable,
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+ .disable = pllb_clk_disable,
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+};
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+
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+static struct clk_init_data clk_pllb_init = {
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+ .name = "pllb",
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+ .ops = &pllb_ops,
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+ .parent_names = pll_clk_parents,
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+ .num_parents = ARRAY_SIZE(pll_clk_parents),
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+};
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+
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static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw)
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{
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return container_of(hw, struct clk_oxnas_gate, hw);
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@@ -262,3 +412,42 @@ static struct platform_driver oxnas_stdc
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},
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};
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builtin_platform_driver(oxnas_stdclk_driver);
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+
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+void __init oxnas_init_plla(struct device_node *np)
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+{
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+ struct clk *clk;
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+ struct clk_oxnas_pll *plla;
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+
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+ plla = kmalloc(sizeof(*plla), GFP_KERNEL);
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+ BUG_ON(!plla);
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+
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+ plla->syscon = syscon_node_to_regmap(of_get_parent(np));
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+ plla->hw.init = &clk_plla_init;
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+ plla->devnode = np;
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+ plla->rstc = NULL;
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+ clk = clk_register(NULL, &plla->hw);
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+ BUG_ON(IS_ERR(clk));
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+ /* mark it as enabled */
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+ clk_prepare_enable(clk);
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+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
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+}
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+CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla);
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+
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+void __init oxnas_init_pllb(struct device_node *np)
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+{
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+ struct clk *clk;
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+ struct clk_oxnas_pll *pllb;
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+
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+ pllb = kmalloc(sizeof(*pllb), GFP_KERNEL);
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+ BUG_ON(!pllb);
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+
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+ pllb->syscon = syscon_node_to_regmap(of_get_parent(np));
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+ pllb->hw.init = &clk_pllb_init;
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+ pllb->devnode = np;
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+ pllb->rstc = NULL;
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+
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+ clk = clk_register(NULL, &pllb->hw);
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+ BUG_ON(IS_ERR(clk));
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+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
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+}
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+CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb);
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--- a/arch/arm/boot/dts/ox820.dtsi
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+++ b/arch/arm/boot/dts/ox820.dtsi
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@@ -60,12 +60,6 @@
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clocks = <&osc>;
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};
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- plla: plla {
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- compatible = "fixed-clock";
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- #clock-cells = <0>;
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- clock-frequency = <850000000>;
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- };
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-
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armclk: armclk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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@@ -265,6 +259,19 @@
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compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
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#clock-cells = <1>;
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};
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+
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+ plla: plla {
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+ compatible = "plxtech,nas782x-plla";
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+ #clock-cells = <0>;
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+ clocks = <&osc>;
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+ };
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+
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+ pllb: pllb {
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+ compatible = "plxtech,nas782x-pllb";
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+ #clock-cells = <0>;
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+ clocks = <&osc>;
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+ resets = <&reset RESET_PLLB>;
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+ };
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};
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};
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@@ -286,6 +293,13 @@
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clocks = <&armclk>;
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};
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+ watchdog@620 {
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+ compatible = "mpcore_wdt";
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+ reg = <0x620 0x20>;
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+ interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
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+ clocks = <&armclk>;
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+ };
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+
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gic: gic@1000 {
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compatible = "arm,arm11mp-gic";
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interrupt-controller;
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