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71 lines
2.0 KiB
Diff
71 lines
2.0 KiB
Diff
From 552ed4955c1fee1109bf5ba137dc35a411a1448c Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Fri, 1 Jun 2018 02:41:15 +0200
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Subject: [PATCH] arm: ox820: remove left-overs
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/clk/clk-oxnas.c | 2 --
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include/dt-bindings/clock/oxsemi,ox820.h | 32 +++++++++++-------------
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2 files changed, 14 insertions(+), 20 deletions(-)
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diff --git a/drivers/clk/clk-oxnas.c b/drivers/clk/clk-oxnas.c
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index e51e0023fc6e..da6af71649de 100644
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--- a/drivers/clk/clk-oxnas.c
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+++ b/drivers/clk/clk-oxnas.c
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@@ -40,8 +40,6 @@ struct oxnas_stdclk_data {
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struct clk_hw_onecell_data *onecell_data;
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struct clk_oxnas_gate **gates;
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unsigned int ngates;
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- struct clk_oxnas_pll **plls;
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- unsigned int nplls;
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};
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/* Regmap offsets */
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diff --git a/include/dt-bindings/clock/oxsemi,ox820.h b/include/dt-bindings/clock/oxsemi,ox820.h
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index f661ecc8d760..35b44ca1b104 100644
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--- a/include/dt-bindings/clock/oxsemi,ox820.h
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+++ b/include/dt-bindings/clock/oxsemi,ox820.h
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@@ -17,24 +17,20 @@
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#ifndef DT_CLOCK_OXSEMI_OX820_H
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#define DT_CLOCK_OXSEMI_OX820_H
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-/* PLLs */
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-#define CLK_820_PLLA 0
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-#define CLK_820_PLLB 1
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-
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/* Gate Clocks */
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-#define CLK_820_LEON 2
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-#define CLK_820_DMA_SGDMA 3
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-#define CLK_820_CIPHER 4
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-#define CLK_820_SD 5
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-#define CLK_820_SATA 6
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-#define CLK_820_AUDIO 7
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-#define CLK_820_USBMPH 8
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-#define CLK_820_ETHA 9
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-#define CLK_820_PCIEA 10
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-#define CLK_820_NAND 11
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-#define CLK_820_PCIEB 12
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-#define CLK_820_ETHB 13
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-#define CLK_820_REF600 14
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-#define CLK_820_USBDEV 15
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+#define CLK_820_LEON 0
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+#define CLK_820_DMA_SGDMA 1
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+#define CLK_820_CIPHER 2
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+#define CLK_820_SD 3
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+#define CLK_820_SATA 4
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+#define CLK_820_AUDIO 5
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+#define CLK_820_USBMPH 6
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+#define CLK_820_ETHA 7
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+#define CLK_820_PCIEA 8
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+#define CLK_820_NAND 9
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+#define CLK_820_PCIEB 10
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+#define CLK_820_ETHB 11
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+#define CLK_820_REF600 12
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+#define CLK_820_USBDEV 13
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#endif /* DT_CLOCK_OXSEMI_OX820_H */
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--
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2.17.1
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