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211 lines
6.7 KiB
Diff
211 lines
6.7 KiB
Diff
From 107ff718dad1c8f6abbf6247d6796a4535b71276 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 14 Dec 2015 23:50:53 +0100
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Subject: [PATCH 509/513] net-next: mediatek: add support for mt7621
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Add support for SoCs from the mt7620 family. This include mt7620 and mt7621.
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These all have one dedicated external gbit port and a builtin 5 port 100mbit
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switch. Additionally one of the 5 switch ports can be changed to become an
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additional gbit port that we can attach a phy to. This patch includes
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rudimentary code to power up the switch. There are a lot of magic values
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that get written to the switch and the internal phys. These values come
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straight from the SDK driver.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
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Signed-off-by: Michael Lee <igvtee@gmail.com>
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---
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drivers/net/ethernet/mediatek/soc_mt7621.c | 186 ++++++++++++++++++++++++++++
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1 file changed, 186 insertions(+)
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create mode 100644 drivers/net/ethernet/mediatek/soc_mt7621.c
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--- /dev/null
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+++ b/drivers/net/ethernet/mediatek/soc_mt7621.c
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@@ -0,0 +1,186 @@
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+/* This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; version 2 of the License
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
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+ * Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
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+ * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/if_vlan.h>
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+#include <linux/of_net.h>
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+
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+#include <asm/mach-ralink/ralink_regs.h>
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+
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+#include "mtk_eth_soc.h"
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+#include "gsw_mt7620.h"
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+#include "mt7530.h"
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+#include "mdio.h"
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+
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+#define MT7620A_CDMA_CSG_CFG 0x400
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+#define MT7621_CDMP_IG_CTRL (MT7620A_CDMA_CSG_CFG + 0x00)
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+#define MT7621_CDMP_EG_CTRL (MT7620A_CDMA_CSG_CFG + 0x04)
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+#define MT7621_RESET_FE BIT(6)
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+#define MT7621_L4_VALID BIT(24)
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+
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+#define MT7621_TX_DMA_UDF BIT(19)
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+#define MT7621_TX_DMA_FPORT BIT(25)
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+
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+#define CDMA_ICS_EN BIT(2)
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+#define CDMA_UCS_EN BIT(1)
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+#define CDMA_TCS_EN BIT(0)
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+
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+#define GDMA_ICS_EN BIT(22)
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+#define GDMA_TCS_EN BIT(21)
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+#define GDMA_UCS_EN BIT(20)
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+
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+/* frame engine counters */
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+#define MT7621_REG_MIB_OFFSET 0x2000
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+#define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
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+#define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
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+#define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40)
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+
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+#define GSW_REG_GDMA1_MAC_ADRL 0x508
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+#define GSW_REG_GDMA1_MAC_ADRH 0x50C
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+
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+#define MT7621_FE_RST_GL (FE_FE_OFFSET + 0x04)
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+#define MT7620_FE_INT_STATUS2 (FE_FE_OFFSET + 0x08)
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+
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+/* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
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+ * but after test it should be BIT(13).
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+ */
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+#define MT7620_FE_GDM1_AF BIT(13)
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+#define MT7621_FE_GDM1_AF BIT(28)
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+#define MT7621_FE_GDM2_AF BIT(29)
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+
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+static const u16 mt7621_reg_table[FE_REG_COUNT] = {
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+ [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
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+ [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
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+ [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
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+ [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
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+ [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
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+ [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
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+ [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
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+ [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
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+ [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
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+ [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
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+ [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
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+ [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
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+ [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
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+ [FE_REG_FE_DMA_VID_BASE] = 0,
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+ [FE_REG_FE_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
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+ [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
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+ [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
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+};
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+
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+static int mt7621_gsw_config(struct fe_priv *priv)
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+{
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+ if (priv->mii_bus && priv->mii_bus->phy_map[0x1f])
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+ mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
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+
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+ return 0;
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+}
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+
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+static void mt7621_fe_reset(void)
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+{
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+ fe_reset(MT7621_RESET_FE);
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+}
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+
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+static void mt7621_rxcsum_config(bool enable)
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+{
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+ if (enable)
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+ fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
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+ GDMA_TCS_EN | GDMA_UCS_EN),
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+ MT7620A_GDMA1_FWD_CFG);
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+ else
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+ fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
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+ GDMA_TCS_EN | GDMA_UCS_EN),
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+ MT7620A_GDMA1_FWD_CFG);
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+}
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+
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+static void mt7621_rxvlan_config(bool enable)
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+{
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+ if (enable)
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+ fe_w32(1, MT7621_CDMP_EG_CTRL);
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+ else
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+ fe_w32(0, MT7621_CDMP_EG_CTRL);
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+}
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+
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+static int mt7621_fwd_config(struct fe_priv *priv)
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+{
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+ struct net_device *dev = priv_netdev(priv);
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+
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+ fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff,
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+ MT7620A_GDMA1_FWD_CFG);
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+
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+ /* mt7621 doesn't have txcsum config */
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+ mt7621_rxcsum_config((dev->features & NETIF_F_RXCSUM));
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+ mt7621_rxvlan_config((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
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+ (priv->flags & FE_FLAG_RX_VLAN_CTAG));
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+
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+ return 0;
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+}
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+
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+static void mt7621_tx_dma(struct fe_tx_dma *txd)
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+{
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+ txd->txd4 = MT7621_TX_DMA_FPORT;
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+}
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+
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+static void mt7621_init_data(struct fe_soc_data *data,
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+ struct net_device *netdev)
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+{
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+ struct fe_priv *priv = netdev_priv(netdev);
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+
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+ priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
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+ FE_FLAG_RX_SG_DMA | FE_FLAG_NAPI_WEIGHT |
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+ FE_FLAG_HAS_SWITCH;
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+
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+ netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
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+ NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_SG | NETIF_F_TSO |
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+ NETIF_F_TSO6 | NETIF_F_IPV6_CSUM;
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+}
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+
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+static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
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+{
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&priv->page_lock, flags);
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+ fe_w32((mac[0] << 8) | mac[1], GSW_REG_GDMA1_MAC_ADRH);
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+ fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
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+ GSW_REG_GDMA1_MAC_ADRL);
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+ spin_unlock_irqrestore(&priv->page_lock, flags);
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+}
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+
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+static struct fe_soc_data mt7621_data = {
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+ .init_data = mt7621_init_data,
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+ .reset_fe = mt7621_fe_reset,
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+ .set_mac = mt7621_set_mac,
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+ .fwd_config = mt7621_fwd_config,
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+ .tx_dma = mt7621_tx_dma,
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+ .switch_init = mtk_gsw_init,
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+ .switch_config = mt7621_gsw_config,
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+ .reg_table = mt7621_reg_table,
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+ .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
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+ .rx_int = RT5350_RX_DONE_INT,
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+ .tx_int = RT5350_TX_DONE_INT,
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+ .status_int = (MT7621_FE_GDM1_AF | MT7621_FE_GDM2_AF),
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+ .checksum_bit = MT7621_L4_VALID,
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+ .has_carrier = mt7620_has_carrier,
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+ .mdio_read = mt7620_mdio_read,
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+ .mdio_write = mt7620_mdio_write,
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+ .mdio_adjust_link = mt7620_mdio_link_adjust,
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+};
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+
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+const struct of_device_id of_fe_match[] = {
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+ { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
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+ {},
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+};
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+
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+MODULE_DEVICE_TABLE(of, of_fe_match);
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