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305 lines
11 KiB
C
305 lines
11 KiB
C
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __INCmvCpuIfRegsh
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#define __INCmvCpuIfRegsh
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/****************************************/
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/* ARM Control and Status Registers Map */
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/****************************************/
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#define CPU_CONFIG_REG 0x20100
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#define CPU_CTRL_STAT_REG 0x20104
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#define CPU_RSTOUTN_MASK_REG 0x20108
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#define CPU_SYS_SOFT_RST_REG 0x2010C
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#define CPU_AHB_MBUS_CAUSE_INT_REG 0x20110
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#define CPU_AHB_MBUS_MASK_INT_REG 0x20114
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#define CPU_FTDLL_CONFIG_REG 0x20120
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#define CPU_L2_CONFIG_REG 0x20128
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/* ARM Configuration register */
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/* CPU_CONFIG_REG (CCR) */
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/* Reset vector location */
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#define CCR_VEC_INIT_LOC_OFFS 1
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#define CCR_VEC_INIT_LOC_MASK BIT1
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/* reset at 0x00000000 */
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#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS)
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/* reset at 0xFFFF0000 */
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#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS)
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#define CCR_AHB_ERROR_PROP_OFFS 2
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#define CCR_AHB_ERROR_PROP_MASK BIT2
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/* Erros are not propogated to AHB */
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#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS)
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/* Erros are propogated to AHB */
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#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS)
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#define CCR_ENDIAN_INIT_OFFS 3
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#define CCR_ENDIAN_INIT_MASK BIT3
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#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS)
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#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS)
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#define CCR_INCR_EN_OFFS 4
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#define CCR_INCR_EN_MASK BIT4
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#define CCR_INCR_EN BIT4
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#define CCR_NCB_BLOCKING_OFFS 5
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#define CCR_NCB_BLOCKING_MASK (1 << CCR_NCB_BLOCKING_OFFS)
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#define CCR_NCB_BLOCKING_NON (0 << CCR_NCB_BLOCKING_OFFS)
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#define CCR_NCB_BLOCKING_EN (1 << CCR_NCB_BLOCKING_OFFS)
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#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8
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#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS)
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#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12
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#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)
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#define CCR_ICACH_PREF_BUF_ENABLE BIT16
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#define CCR_DCACH_PREF_BUF_ENABLE BIT17
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/* Ratio options for CPU to DDR for 6281/6192/6190 */
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#define CPU_2_DDR_CLK_1x3 4
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#define CPU_2_DDR_CLK_1x4 6
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/* Ratio options for CPU to DDR for 6281 only */
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#define CPU_2_DDR_CLK_2x9 7
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#define CPU_2_DDR_CLK_1x5 8
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#define CPU_2_DDR_CLK_1x6 9
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/* Ratio options for CPU to DDR for 6180 only */
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#define CPU_2_DDR_CLK_1x3_1 0x5
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#define CPU_2_DDR_CLK_1x4_1 0x6
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/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */
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/* CPU to Mbus-L Tick Sample fields in CPU config register */
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#define TICK_DRV_1x1 0
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#define TICK_DRV_1x2 0
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#define TICK_DRV_1x3 1
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#define TICK_DRV_1x4 2
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#define TICK_SMPL_1x1 0
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#define TICK_SMPL_1x2 1
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#define TICK_SMPL_1x3 0
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#define TICK_SMPL_1x4 0
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#define CPU_2_MBUSL_DDR_CLK_1x2 \
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((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \
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(TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
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#define CPU_2_MBUSL_DDR_CLK_1x3 \
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((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \
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(TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
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#define CPU_2_MBUSL_DDR_CLK_1x4 \
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((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \
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(TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
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/* ARM Control and Status register */
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/* CPU_CTRL_STAT_REG (CCSR) */
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/*
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This is used to block PCI express\PCI from access Socrates/Feroceon GP
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while ARM boot is still in progress
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*/
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#define CCSR_PCI_ACCESS_OFFS 0
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#define CCSR_PCI_ACCESS_MASK BIT0
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#define CCSR_PCI_ACCESS_ENABLE (0 << CCSR_PCI_ACCESS_OFFS)
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#define CCSR_PCI_ACCESS_DISBALE (1 << CCSR_PCI_ACCESS_OFFS)
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#define CCSR_ARM_RESET BIT1
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#define CCSR_SELF_INT BIT2
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#define CCSR_BIG_ENDIAN BIT15
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/* RSTOUTn Mask Register */
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/* CPU_RSTOUTN_MASK_REG (CRMR) */
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#define CRMR_PEX_RST_OUT_OFFS 0
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#define CRMR_PEX_RST_OUT_MASK BIT0
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#define CRMR_PEX_RST_OUT_ENABLE (1 << CRMR_PEX_RST_OUT_OFFS)
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#define CRMR_PEX_RST_OUT_DISABLE (0 << CRMR_PEX_RST_OUT_OFFS)
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#define CRMR_WD_RST_OUT_OFFS 1
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#define CRMR_WD_RST_OUT_MASK BIT1
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#define CRMR_WD_RST_OUT_ENABLE (1 << CRMR_WD_RST_OUT_OFFS)
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#define CRMR_WD_RST_OUT_DISBALE (0 << CRMR_WD_RST_OUT_OFFS)
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#define CRMR_SOFT_RST_OUT_OFFS 2
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#define CRMR_SOFT_RST_OUT_MASK BIT2
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#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS)
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#define CRMR_SOFT_RST_OUT_DISBALE (0 << CRMR_SOFT_RST_OUT_OFFS)
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/* System Software Reset Register */
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/* CPU_SYS_SOFT_RST_REG (CSSRR) */
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#define CSSRR_SYSTEM_SOFT_RST BIT0
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/* AHB to Mbus Bridge Interrupt Cause Register*/
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/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */
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#define CAMCIR_ARM_SELF_INT BIT0
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#define CAMCIR_ARM_TIMER0_INT_REQ BIT1
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#define CAMCIR_ARM_TIMER1_INT_REQ BIT2
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#define CAMCIR_ARM_WD_TIMER_INT_REQ BIT3
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/* AHB to Mbus Bridge Interrupt Mask Register*/
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/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */
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#define CAMCIR_ARM_SELF_INT_OFFS 0
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#define CAMCIR_ARM_SELF_INT_MASK BIT0
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#define CAMCIR_ARM_SELF_INT_EN (1 << CAMCIR_ARM_SELF_INT_OFFS)
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#define CAMCIR_ARM_SELF_INT_DIS (0 << CAMCIR_ARM_SELF_INT_OFFS)
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#define CAMCIR_ARM_TIMER0_INT_REQ_OFFS 1
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#define CAMCIR_ARM_TIMER0_INT_REQ_MASK BIT1
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#define CAMCIR_ARM_TIMER0_INT_REQ_EN (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS)
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#define CAMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS)
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#define CAMCIR_ARM_TIMER1_INT_REQ_OFFS 2
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#define CAMCIR_ARM_TIMER1_INT_REQ_MASK BIT2
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#define CAMCIR_ARM_TIMER1_INT_REQ_EN (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS)
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#define CAMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS)
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#define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3
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#define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3
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#define CAMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS)
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#define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS)
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/* CPU FTDLL Config register (CFCR) fields */
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#define CFCR_FTDLL_ICACHE_TAG_OFFS 0
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#define CFCR_FTDLL_ICACHE_TAG_MASK (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS)
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#define CFCR_FTDLL_DCACHE_TAG_OFFS 8
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#define CFCR_FTDLL_DCACHE_TAG_MASK (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS)
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#define CFCR_FTDLL_OVERWRITE_ENABLE (1 << 15)
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/* For Orion 2 D2 only */
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#define CFCR_MRVL_CPU_ID_OFFS 16
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#define CFCR_MRVL_CPU_ID_MASK (0x1 << CFCR_MRVL_CPU_ID_OFFS)
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#define CFCR_ARM_CPU_ID (0x0 << CFCR_MRVL_CPU_ID_OFFS)
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#define CFCR_MRVL_CPU_ID (0x1 << CFCR_MRVL_CPU_ID_OFFS)
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#define CFCR_VFP_SUB_ARC_NUM_OFFS 7
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#define CFCR_VFP_SUB_ARC_NUM_MASK (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS)
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#define CFCR_VFP_SUB_ARC_NUM_1 (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS)
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#define CFCR_VFP_SUB_ARC_NUM_2 (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS)
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/* CPU_L2_CONFIG_REG fields */
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#ifdef MV_CPU_LE
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#define CL2CR_L2_ECC_EN_OFFS 2
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#define CL2CR_L2_WT_MODE_OFFS 4
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#else
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#define CL2CR_L2_ECC_EN_OFFS 26
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#define CL2CR_L2_WT_MODE_OFFS 28
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#endif
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#define CL2CR_L2_ECC_EN_MASK (1 << CL2CR_L2_ECC_EN_OFFS)
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#define CL2CR_L2_WT_MODE_MASK (1 << CL2CR_L2_WT_MODE_OFFS)
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/*******************************************/
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/* Main Interrupt Controller Registers Map */
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/*******************************************/
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#define CPU_MAIN_INT_CAUSE_REG 0x20200
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#define CPU_MAIN_IRQ_MASK_REG 0x20204
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#define CPU_MAIN_FIQ_MASK_REG 0x20208
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#define CPU_ENPOINT_MASK_REG 0x2020C
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#define CPU_MAIN_INT_CAUSE_HIGH_REG 0x20210
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#define CPU_MAIN_IRQ_MASK_HIGH_REG 0x20214
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#define CPU_MAIN_FIQ_MASK_HIGH_REG 0x20218
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#define CPU_ENPOINT_MASK_HIGH_REG 0x2021C
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/*******************************************/
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/* ARM Doorbell Registers Map */
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/*******************************************/
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#define CPU_HOST_TO_ARM_DRBL_REG 0x20400
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#define CPU_HOST_TO_ARM_MASK_REG 0x20404
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#define CPU_ARM_TO_HOST_DRBL_REG 0x20408
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#define CPU_ARM_TO_HOST_MASK_REG 0x2040C
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/* CPU control register map */
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/* Set bits means value is about to change according to new value */
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#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | CCR_AHB_ERROR_PROP_MASK)
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#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00)
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/* CPU Control and status defaults */
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#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK)
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#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE)
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#endif /* __INCmvCpuIfRegsh */
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