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321 lines
10 KiB
C
321 lines
10 KiB
C
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#include "cpu/mvCpu.h"
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#include "ctrlEnv/mvCtrlEnvLib.h"
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#include "ctrlEnv/mvCtrlEnvRegs.h"
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#include "ctrlEnv/sys/mvCpuIfRegs.h"
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/* defines */
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#ifdef MV_DEBUG
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#define DB(x) x
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#else
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#define DB(x)
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#endif
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/* locals */
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/*******************************************************************************
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* mvCpuPclkGet - Get the CPU pClk (pipe clock)
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*
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* DESCRIPTION:
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* This routine extract the CPU core clock.
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*
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* INPUT:
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* None.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* 32bit clock cycles in MHertz.
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*
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*******************************************************************************/
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/* 6180 have different clk reset sampling */
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static MV_U32 mvCpu6180PclkGet(MV_VOID)
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{
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MV_U32 tmpPClkRate=0;
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MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL;
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tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET);
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tmpPClkRate = tmpPClkRate & MSAR_CPUCLCK_MASK_6180;
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tmpPClkRate = tmpPClkRate >> MSAR_CPUCLCK_OFFS_6180;
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tmpPClkRate = cpu6180_ddr_l2_CLK[tmpPClkRate].cpuClk;
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return tmpPClkRate;
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}
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MV_U32 mvCpuPclkGet(MV_VOID)
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{
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#if defined(PCLCK_AUTO_DETECT)
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MV_U32 tmpPClkRate=0;
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MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL;
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if(mvCtrlModelGet() == MV_6180_DEV_ID)
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return mvCpu6180PclkGet();
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tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET);
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tmpPClkRate = MSAR_CPUCLCK_EXTRACT(tmpPClkRate);
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tmpPClkRate = cpuCLK[tmpPClkRate];
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return tmpPClkRate;
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#else
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return MV_DEFAULT_PCLK
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#endif
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}
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/*******************************************************************************
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* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock)
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*
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* DESCRIPTION:
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* This routine extract the CPU L2 clock.
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*
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* RETURN:
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* 32bit clock cycles in Hertz.
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*
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*******************************************************************************/
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static MV_U32 mvCpu6180L2ClkGet(MV_VOID)
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{
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MV_U32 L2ClkRate=0;
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MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL;
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L2ClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET);
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L2ClkRate = L2ClkRate & MSAR_CPUCLCK_MASK_6180;
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L2ClkRate = L2ClkRate >> MSAR_CPUCLCK_OFFS_6180;
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L2ClkRate = _cpu6180_ddr_l2_CLK[L2ClkRate].l2Clk;
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return L2ClkRate;
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}
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MV_U32 mvCpuL2ClkGet(MV_VOID)
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{
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#ifdef L2CLK_AUTO_DETECT
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MV_U32 L2ClkRate, tmp, pClkRate, indexL2Rtio;
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MV_U32 L2Rtio[][2] = MV_L2_CLCK_RTIO_TBL;
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if(mvCtrlModelGet() == MV_6180_DEV_ID)
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return mvCpu6180L2ClkGet();
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pClkRate = mvCpuPclkGet();
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tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET);
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indexL2Rtio = MSAR_L2CLCK_EXTRACT(tmp);
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L2ClkRate = ((pClkRate * L2Rtio[indexL2Rtio][1]) / L2Rtio[indexL2Rtio][0]);
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return L2ClkRate;
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#else
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return MV_BOARD_DEFAULT_L2CLK;
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#endif
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}
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/*******************************************************************************
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* mvCpuNameGet - Get CPU name
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*
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* DESCRIPTION:
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* This function returns a string describing the CPU model and revision.
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*
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* INPUT:
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* None.
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*
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* OUTPUT:
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* pNameBuff - Buffer to contain board name string. Minimum size 32 chars.
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*
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* RETURN:
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* None.
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*******************************************************************************/
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MV_VOID mvCpuNameGet(char *pNameBuff)
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{
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MV_U32 cpuModel;
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cpuModel = mvOsCpuPartGet();
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/* The CPU module is indicated in the Processor Version Register (PVR) */
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switch(cpuModel)
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{
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case CPU_PART_MRVL131:
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mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet());
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break;
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case CPU_PART_ARM926:
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mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet());
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break;
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case CPU_PART_ARM946:
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mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet());
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break;
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default:
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mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet());
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break;
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} /* switch */
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return;
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}
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#define MV_PROC_STR_SIZE 50
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static void mvCpuIfGetL2EccMode(MV_8 *buf)
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{
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MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG);
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if (regVal & BIT2)
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mvOsSPrintf(buf, "L2 ECC Enabled");
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else
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mvOsSPrintf(buf, "L2 ECC Disabled");
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}
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static void mvCpuIfGetL2Mode(MV_8 *buf)
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{
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MV_U32 regVal = 0;
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__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
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if (regVal & BIT22)
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mvOsSPrintf(buf, "L2 Enabled");
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else
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mvOsSPrintf(buf, "L2 Disabled");
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}
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static void mvCpuIfGetL2PrefetchMode(MV_8 *buf)
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{
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MV_U32 regVal = 0;
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__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
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if (regVal & BIT24)
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mvOsSPrintf(buf, "L2 Prefetch Disabled");
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else
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mvOsSPrintf(buf, "L2 Prefetch Enabled");
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}
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static void mvCpuIfGetWriteAllocMode(MV_8 *buf)
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{
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MV_U32 regVal = 0;
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__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
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if (regVal & BIT28)
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mvOsSPrintf(buf, "Write Allocate Enabled");
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else
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mvOsSPrintf(buf, "Write Allocate Disabled");
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}
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static void mvCpuIfGetCpuStreamMode(MV_8 *buf)
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{
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MV_U32 regVal = 0;
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__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
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if (regVal & BIT29)
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mvOsSPrintf(buf, "CPU Streaming Enabled");
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else
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mvOsSPrintf(buf, "CPU Streaming Disabled");
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}
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static void mvCpuIfPrintCpuRegs(void)
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{
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MV_U32 regVal = 0;
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__asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */
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mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal);
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__asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */
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mvOsPrintf("Control Reg = 0x%x\n",regVal);
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__asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */
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mvOsPrintf("ID Code Reg = 0x%x\n",regVal);
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__asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */
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mvOsPrintf("Cache Type Reg = 0x%x\n",regVal);
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}
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MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index)
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{
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MV_U32 count = 0;
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MV_8 L2_ECC_str[MV_PROC_STR_SIZE];
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MV_8 L2_En_str[MV_PROC_STR_SIZE];
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MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE];
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MV_8 Write_Alloc_str[MV_PROC_STR_SIZE];
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MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE];
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mvCpuIfGetL2Mode(L2_En_str);
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mvCpuIfGetL2EccMode(L2_ECC_str);
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mvCpuIfGetL2PrefetchMode(L2_Prefetch_str);
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mvCpuIfGetWriteAllocMode(Write_Alloc_str);
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mvCpuIfGetCpuStreamMode(Cpu_Stream_str);
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mvCpuIfPrintCpuRegs();
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count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str);
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count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str);
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count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str);
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count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str);
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count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str);
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return count;
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}
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MV_U32 whoAmI(MV_VOID)
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{
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return 0;
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}
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