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263 lines
11 KiB
C
263 lines
11 KiB
C
/*******************************************************************************
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Copyright (C) Marvell International Ltd. and its affiliates
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This software file (the "File") is owned and distributed by Marvell
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International Ltd. and/or its affiliates ("Marvell") under the following
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alternative licensing terms. Once you have made an election to distribute the
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File under one of the following license alternatives, please (i) delete this
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introductory statement regarding license alternatives, (ii) delete the two
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license alternatives that you have not elected to use and (iii) preserve the
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Marvell copyright notice above.
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********************************************************************************
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Marvell Commercial License Option
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If you received this File from Marvell and you have entered into a commercial
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license agreement (a "Commercial License") with Marvell, the File is licensed
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to you under the terms of the applicable Commercial License.
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********************************************************************************
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Marvell GPL License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File in accordance with the terms and conditions of the General
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Public License Version 2, June 1991 (the "GPL License"), a copy of which is
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available along with the File in the license.txt file or by writing to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
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on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
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THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
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WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
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DISCLAIMED. The GPL License provides additional details about this warranty
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disclaimer.
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********************************************************************************
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Marvell BSD License Option
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If you received this File from Marvell, you may opt to use, redistribute and/or
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modify this File under the following licensing terms.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Marvell nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef __INCmvBoardEnvSpech
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#define __INCmvBoardEnvSpech
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#include "mvSysHwConfig.h"
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/* For future use */
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#define BD_ID_DATA_START_OFFS 0x0
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#define BD_DETECT_SEQ_OFFS 0x0
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#define BD_SYS_NUM_OFFS 0x4
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#define BD_NAME_OFFS 0x8
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/* I2C bus addresses */
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#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */
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#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT
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#define MV_BOARD_DIMM0_I2C_ADDR 0x56
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#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT
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#define MV_BOARD_DIMM1_I2C_ADDR 0x54
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#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT
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#define MV_BOARD_EEPROM_I2C_ADDR 0x51
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#define MV_BOARD_EEPROM_I2C_ADDR_TYPE ADDR7_BIT
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#define MV_BOARD_MAIN_EEPROM_I2C_ADDR 0x50
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#define MV_BOARD_MAIN_EEPROM_I2C_ADDR_TYPE ADDR7_BIT
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#define MV_BOARD_MUX_I2C_ADDR_ENTRY 0x2
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#define MV_BOARD_DIMM_I2C_CHANNEL 0x0
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#define BOOT_FLASH_INDEX 0
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#define MAIN_FLASH_INDEX 1
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#define BOARD_ETH_START_PORT_NUM 0
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/* Supported clocks */
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#define MV_BOARD_TCLK_100MHZ 100000000
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#define MV_BOARD_TCLK_125MHZ 125000000
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#define MV_BOARD_TCLK_133MHZ 133333333
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#define MV_BOARD_TCLK_150MHZ 150000000
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#define MV_BOARD_TCLK_166MHZ 166666667
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#define MV_BOARD_TCLK_200MHZ 200000000
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#define MV_BOARD_SYSCLK_100MHZ 100000000
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#define MV_BOARD_SYSCLK_125MHZ 125000000
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#define MV_BOARD_SYSCLK_133MHZ 133333333
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#define MV_BOARD_SYSCLK_150MHZ 150000000
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#define MV_BOARD_SYSCLK_166MHZ 166666667
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#define MV_BOARD_SYSCLK_200MHZ 200000000
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#define MV_BOARD_SYSCLK_233MHZ 233333333
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#define MV_BOARD_SYSCLK_250MHZ 250000000
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#define MV_BOARD_SYSCLK_267MHZ 266666667
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#define MV_BOARD_SYSCLK_300MHZ 300000000
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#define MV_BOARD_SYSCLK_333MHZ 333333334
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#define MV_BOARD_SYSCLK_400MHZ 400000000
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#define MV_BOARD_REFCLK_25MHZ 25000000
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/* Board specific */
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/* =============================== */
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/* boards ID numbers */
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#define BOARD_ID_BASE 0x0
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/* New board ID numbers */
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#define DB_88F6281A_BP_ID (BOARD_ID_BASE)
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#define DB_88F6281_BP_MLL_ID 1680
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#define RD_88F6281A_ID (BOARD_ID_BASE+0x1)
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#define RD_88F6281_MLL_ID 1682
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#define DB_88F6192A_BP_ID (BOARD_ID_BASE+0x2)
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#define RD_88F6192A_ID (BOARD_ID_BASE+0x3)
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#define RD_88F6192_MLL_ID 1681
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#define DB_88F6180A_BP_ID (BOARD_ID_BASE+0x4)
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#define DB_88F6190A_BP_ID (BOARD_ID_BASE+0x5)
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#define RD_88F6190A_ID (BOARD_ID_BASE+0x6)
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#define RD_88F6281A_PCAC_ID (BOARD_ID_BASE+0x7)
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#define DB_CUSTOMER_ID (BOARD_ID_BASE+0x8)
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#define SHEEVA_PLUG_ID (BOARD_ID_BASE+0x9)
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#define MV_MAX_BOARD_ID (SHEEVA_PLUG_ID + 1)
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/* DB-88F6281A-BP */
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#if defined(MV_NAND)
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#define DB_88F6281A_MPP0_7 0x21111111
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#else
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#define DB_88F6281A_MPP0_7 0x21112220
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#endif
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#define DB_88F6281A_MPP8_15 0x11113311
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#define DB_88F6281A_MPP16_23 0x00551111
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#define DB_88F6281A_MPP24_31 0x00000000
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#define DB_88F6281A_MPP32_39 0x00000000
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#define DB_88F6281A_MPP40_47 0x00000000
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#define DB_88F6281A_MPP48_55 0x00000000
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#define DB_88F6281A_OE_LOW 0x0
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#if defined(MV_TDM_5CHANNELS)
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#define DB_88F6281A_OE_HIGH (BIT6)
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#else
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#define DB_88F6281A_OE_HIGH 0x0
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#endif
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#define DB_88F6281A_OE_VAL_LOW 0x0
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#define DB_88F6281A_OE_VAL_HIGH 0x0
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/* RD-88F6281A */
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#if defined(MV_NAND)
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#define RD_88F6281A_MPP0_7 0x21111111
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#else
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#define RD_88F6281A_MPP0_7 0x21112220
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#endif
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#define RD_88F6281A_MPP8_15 0x11113311
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#define RD_88F6281A_MPP16_23 0x33331111
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#define RD_88F6281A_MPP24_31 0x33003333
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#define RD_88F6281A_MPP32_39 0x20440533
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#define RD_88F6281A_MPP40_47 0x22202222
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#define RD_88F6281A_MPP48_55 0x00000002
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#define RD_88F6281A_OE_LOW (BIT28 | BIT29)
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#define RD_88F6281A_OE_HIGH (BIT3 | BIT6 | BIT17)
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#define RD_88F6281A_OE_VAL_LOW 0x0
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#define RD_88F6281A_OE_VAL_HIGH 0x0
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/* DB-88F6192A-BP */
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#if defined(MV_NAND)
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#define DB_88F6192A_MPP0_7 0x21111111
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#else
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#define DB_88F6192A_MPP0_7 0x21112220
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#endif
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#define DB_88F6192A_MPP8_15 0x11113311
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#define DB_88F6192A_MPP16_23 0x00501111
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#define DB_88F6192A_MPP24_31 0x00000000
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#define DB_88F6192A_MPP32_35 0x00000000
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#define DB_88F6192A_OE_LOW (BIT22 | BIT23)
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#define DB_88F6192A_OE_HIGH 0x0
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#define DB_88F6192A_OE_VAL_LOW 0x0
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#define DB_88F6192A_OE_VAL_HIGH 0x0
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/* RD-88F6192A */
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#define RD_88F6192A_MPP0_7 0x01222222
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#define RD_88F6192A_MPP8_15 0x00000011
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#define RD_88F6192A_MPP16_23 0x05550000
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#define RD_88F6192A_MPP24_31 0x0
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#define RD_88F6192A_MPP32_35 0x0
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#define RD_88F6192A_OE_LOW (BIT11 | BIT14 | BIT24 | BIT25 | BIT26 | BIT27 | BIT30 | BIT31)
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#define RD_88F6192A_OE_HIGH (BIT0 | BIT2)
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#define RD_88F6192A_OE_VAL_LOW 0x18400
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#define RD_88F6192A_OE_VAL_HIGH 0x8
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/* DB-88F6180A-BP */
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#if defined(MV_NAND)
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#define DB_88F6180A_MPP0_7 0x21111111
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#else
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#define DB_88F6180A_MPP0_7 0x01112222
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#endif
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#define DB_88F6180A_MPP8_15 0x11113311
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#define DB_88F6180A_MPP16_23 0x00001111
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#define DB_88F6180A_MPP24_31 0x0
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#define DB_88F6180A_MPP32_39 0x4444c000
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#define DB_88F6180A_MPP40_44 0x00044444
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#define DB_88F6180A_OE_LOW 0x0
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#define DB_88F6180A_OE_HIGH 0x0
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#define DB_88F6180A_OE_VAL_LOW 0x0
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#define DB_88F6180A_OE_VAL_HIGH 0x0
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/* RD-88F6281A_PCAC */
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#define RD_88F6281A_PCAC_MPP0_7 0x21111111
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#define RD_88F6281A_PCAC_MPP8_15 0x00003311
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#define RD_88F6281A_PCAC_MPP16_23 0x00001100
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#define RD_88F6281A_PCAC_MPP24_31 0x00000000
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#define RD_88F6281A_PCAC_MPP32_39 0x00000000
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#define RD_88F6281A_PCAC_MPP40_47 0x00000000
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#define RD_88F6281A_PCAC_MPP48_55 0x00000000
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#define RD_88F6281A_PCAC_OE_LOW 0x0
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#define RD_88F6281A_PCAC_OE_HIGH 0x0
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#define RD_88F6281A_PCAC_OE_VAL_LOW 0x0
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#define RD_88F6281A_PCAC_OE_VAL_HIGH 0x0
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/* SHEEVA PLUG */
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#define RD_SHEEVA_PLUG_MPP0_7 0x01111111
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#define RD_SHEEVA_PLUG_MPP8_15 0x11113322
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#define RD_SHEEVA_PLUG_MPP16_23 0x00001111
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#define RD_SHEEVA_PLUG_MPP24_31 0x00100000
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#define RD_SHEEVA_PLUG_MPP32_39 0x00000000
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#define RD_SHEEVA_PLUG_MPP40_47 0x00000000
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#define RD_SHEEVA_PLUG_MPP48_55 0x00000000
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#define RD_SHEEVA_PLUG_OE_LOW 0x0
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#define RD_SHEEVA_PLUG_OE_HIGH 0x0
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#define RD_SHEEVA_PLUG_OE_VAL_LOW (BIT29)
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#define RD_SHEEVA_PLUG_OE_VAL_HIGH ((~(BIT17 | BIT16 | BIT15)) | BIT14)
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/* DB-CUSTOMER */
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#define DB_CUSTOMER_MPP0_7 0x21111111
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#define DB_CUSTOMER_MPP8_15 0x00003311
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#define DB_CUSTOMER_MPP16_23 0x00001100
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#define DB_CUSTOMER_MPP24_31 0x00000000
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#define DB_CUSTOMER_MPP32_39 0x00000000
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#define DB_CUSTOMER_MPP40_47 0x00000000
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#define DB_CUSTOMER_MPP48_55 0x00000000
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#define DB_CUSTOMER_OE_LOW 0x0
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#define DB_CUSTOMER_OE_HIGH (~((BIT6) | (BIT7) | (BIT8) | (BIT9)))
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#define DB_CUSTOMER_OE_VAL_LOW 0x0
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#define DB_CUSTOMER_OE_VAL_HIGH 0x0
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#endif /* __INCmvBoardEnvSpech */
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