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410 lines
12 KiB
Diff
410 lines
12 KiB
Diff
From 4d77ad216ad86b3b25c196a189fa28f3e53c3ffd Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 30 Nov 2012 21:32:00 +0100
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Subject: [PATCH 101/123] MIPS: lantiq: adds support for SVIP SoC Family
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---
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arch/mips/kernel/cevt-r4k.c | 4 +-
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arch/mips/lantiq/Kconfig | 4 ++
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arch/mips/lantiq/Makefile | 1 +
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arch/mips/lantiq/Platform | 1 +
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arch/mips/lantiq/clk.c | 7 +++
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arch/mips/lantiq/clk.h | 4 ++
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arch/mips/lantiq/svip/Makefile | 1 +
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arch/mips/lantiq/svip/clk.c | 70 ++++++++++++++++++++++++++
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arch/mips/lantiq/svip/prom.c | 43 ++++++++++++++++
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arch/mips/lantiq/svip/reset.c | 105 +++++++++++++++++++++++++++++++++++++++
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arch/mips/lantiq/svip/sysctrl.c | 81 ++++++++++++++++++++++++++++++
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11 files changed, 320 insertions(+), 1 deletion(-)
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create mode 100644 arch/mips/lantiq/svip/Makefile
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create mode 100644 arch/mips/lantiq/svip/clk.c
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create mode 100644 arch/mips/lantiq/svip/prom.c
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create mode 100644 arch/mips/lantiq/svip/reset.c
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create mode 100644 arch/mips/lantiq/svip/sysctrl.c
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--- a/arch/mips/kernel/cevt-r4k.c
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+++ b/arch/mips/kernel/cevt-r4k.c
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@@ -176,8 +176,10 @@ int __cpuinit r4k_clockevent_init(void)
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if (!cpu_has_counter || !mips_hpt_frequency)
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return -ENXIO;
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- if (!c0_compare_int_usable())
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+ if (!c0_compare_int_usable()) {
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+ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
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return -ENXIO;
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+ }
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/*
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* With vectored interrupts things are getting platform specific.
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--- a/arch/mips/lantiq/Kconfig
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+++ b/arch/mips/lantiq/Kconfig
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@@ -22,6 +22,10 @@ config SOC_FALCON
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bool "FALCON"
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select PINCTRL_FALCON
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+config SOC_SVIP
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+ bool "SVIP"
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+ select MIPS_CPU_SCACHE
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+
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endchoice
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choice
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--- a/arch/mips/lantiq/Makefile
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+++ b/arch/mips/lantiq/Makefile
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@@ -12,3 +12,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
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obj-$(CONFIG_SOC_TYPE_XWAY) += xway/
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obj-$(CONFIG_SOC_FALCON) += falcon/
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+obj-$(CONFIG_SOC_SVIP) += svip/
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--- a/arch/mips/lantiq/Platform
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+++ b/arch/mips/lantiq/Platform
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@@ -7,3 +7,4 @@ cflags-$(CONFIG_LANTIQ) += -I$(srctree)
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load-$(CONFIG_LANTIQ) = 0xffffffff80002000
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cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
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cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
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+cflags-$(CONFIG_SOC_SVIP) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/svip
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--- a/arch/mips/lantiq/clk.c
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+++ b/arch/mips/lantiq/clk.c
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@@ -163,8 +163,15 @@ void __init plat_time_init(void)
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ltq_soc_init();
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clk = clk_get_cpu();
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+#ifdef CONFIG_SOC_SVIP
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+ mips_hpt_frequency = ltq_svip_cpu_hz() / get_counter_resolution();
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+ write_c0_count(0);
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+ write_c0_compare(mips_hpt_frequency / HZ);
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+ enable_irq(MIPS_CPU_TIMER_IRQ);
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+#else
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mips_hpt_frequency = clk_get_rate(clk) / get_counter_resolution();
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write_c0_compare(read_c0_count());
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+#endif
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pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
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clk_put(clk);
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}
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--- a/arch/mips/lantiq/clk.h
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+++ b/arch/mips/lantiq/clk.h
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@@ -75,4 +75,8 @@ extern unsigned long ltq_ar9_fpi_hz(void
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extern unsigned long ltq_vr9_cpu_hz(void);
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extern unsigned long ltq_vr9_fpi_hz(void);
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+extern unsigned long ltq_svip_cpu_hz(void);
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+extern unsigned long ltq_svip_fpi_hz(void);
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+extern unsigned long ltq_svip_io_hz(void);
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+
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#endif
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--- /dev/null
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+++ b/arch/mips/lantiq/svip/Makefile
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@@ -0,0 +1 @@
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+obj-y := prom.o reset.o sysctrl.o clk.o
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--- /dev/null
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+++ b/arch/mips/lantiq/svip/clk.c
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@@ -0,0 +1,70 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/io.h>
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+#include <linux/export.h>
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+#include <linux/init.h>
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+#include <linux/clk.h>
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+
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+#include <asm/time.h>
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+#include <asm/irq.h>
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+#include <asm/div64.h>
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+
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+#include <lantiq_soc.h>
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+
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+#include "../clk.h"
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+
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+#define STATUS_CONFIG_CLK_MODE (0x1 << 1)
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+#define STATUS_CONFIG_CLK_MODE_GET(val) ((((val) & STATUS_CONFIG_CLK_MODE) >> 4) & 0x1)
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+#define STATUS_CONFIG 0x0010
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+
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+#define SYS0_PLL1CR_PLLDIV (0x3)
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+#define SYS0_PLL1CR_PLLDIV_GET(val) ((((val) & SYS0_PLL1CR_PLLDIV) >> 0) & 0x3)
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+#define SYS0_PLL1CR 0x0008
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+
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+#define SYS1_FPICR_FPIDIV (0x1)
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+#define SYS1_FPICR_FPIDIV_GET(val) ((((val) & SYS1_FPICR_FPIDIV) >> 0) & 0x1)
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+#define SYS1_FPICR 0x0014
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+
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+unsigned long ltq_svip_io_hz(void)
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+{
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+ return 200000000; /* 200 MHz */
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+}
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+
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+unsigned long ltq_svip_cpu_hz(void)
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+{
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+ /* Magic BootROM speed location... */
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+ if ((*(u32 *)0x9fc07ff0) == 1)
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+ return *(u32 *)0x9fc07ff4;
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+
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+ if (STATUS_CONFIG_CLK_MODE_GET(ltq_status_r32(STATUS_CONFIG)) == 1) {
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+ /* xT16 */
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+ return 393216000;
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+ } else {
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+ switch (SYS0_PLL1CR_PLLDIV_GET(ltq_sys0_r32(SYS0_PLL1CR))) {
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+ case 3:
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+ return 475000000;
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+ case 2:
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+ return 450000000;
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+ case 1:
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+ return 425000000;
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+ default:
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+ break;
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+ }
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+ }
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+ return 400000000;
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+}
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+
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+unsigned long ltq_svip_fpi_hz(void)
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+{
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+ u32 fbs0_div[2] = {4, 8};
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+ u32 div;
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+
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+ div = SYS1_FPICR_FPIDIV_GET(ltq_sys1_r32(SYS1_FPICR));
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+ return ltq_svip_cpu_hz() / fbs0_div[div];
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+}
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--- /dev/null
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+++ b/arch/mips/lantiq/svip/prom.c
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@@ -0,0 +1,43 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
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+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/kernel.h>
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+#include <asm/io.h>
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+
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+#include <lantiq_soc.h>
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+
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+#include "../prom.h"
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+
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+#define SOC_SVIP "SVIP"
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+
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+#define COMP_SVIP "lantiq,svip"
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+
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+#define PART_SHIFT 12
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+#define PART_MASK 0x0FFFF000
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+#define REV_SHIFT 28
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+#define REV_MASK 0xF0000000
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+
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+void __init ltq_soc_detect(struct ltq_soc_info *i)
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+{
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+ i->partnum = (ltq_r32(LTQ_STATUS_CHIPID) & PART_MASK) >> PART_SHIFT;
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+ i->rev = (ltq_r32(LTQ_STATUS_CHIPID) & REV_MASK) >> REV_SHIFT;
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+ sprintf(i->rev_type, "1.%d", i->rev);
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+
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+ switch (i->partnum) {
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+ case SOC_ID_SVIP:
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+ i->name = SOC_SVIP;
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+ i->type = SOC_TYPE_SVIP;
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+ i->compatible = COMP_SVIP;
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+ break;
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+
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+ default:
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+ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
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+ break;
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+ }
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+}
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--- /dev/null
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+++ b/arch/mips/lantiq/svip/reset.c
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@@ -0,0 +1,105 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/io.h>
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+#include <linux/ioport.h>
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+#include <linux/pm.h>
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+#include <linux/module.h>
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+#include <asm/reboot.h>
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+
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+#include <lantiq_soc.h>
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+
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+#define CPLD_CMDREG3 ((volatile unsigned char*)(KSEG1 + 0x120000f3))
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+
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+#define LTQ_EBU_ADDRSEL2 0x0028
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+#define LTQ_EBU_BUSCON2 0x0068
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+#define LTQ_BOOT_CPU_OFFSET 0x20
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+
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+#define LTQ_L2_SPRAM_BASE (KSEG1 + 0x1F1E8000)
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+#define LTQ_BOOT_RVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \
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+ (cpu * LTQ_BOOT_CPU_OFFSET))
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+
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+#define SYS0_BCR 0x0004
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+#define BMODE_SHIFT 16
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+#define BMODE_MASK 0x1f
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+
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+#define SYS1_CLKCLR 0x0008
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+#define SYS1_RREQR 0x0044
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+#define SYS1_RRLSR 0x0048
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+#define SYS1_RBTR 0x004c
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+#define SYS1_CPU0RSR 0x0060
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+#define SYS1_CPU0RSR_MASK 0x0007
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+
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+/* This function is used by the watchdog driver */
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+int ltq_reset_cause(void)
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+{
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+ return ltq_sys1_r32(SYS1_CPU0RSR) & SYS1_CPU0RSR_MASK;
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+}
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+EXPORT_SYMBOL_GPL(ltq_reset_cause);
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+
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+/* allow platform code to find out what source we booted from */
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+unsigned char ltq_boot_select(void)
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+{
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+ return (ltq_sys0_r32(SYS0_BCR) >> BMODE_SHIFT) & BMODE_MASK;
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+}
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+
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+static void ltq_machine_restart(char *command)
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+{
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+ local_irq_disable();
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+ if (/*mips_machtype == LANTIQ_MACH_EASY33016 ||
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+ mips_machtype == LANTIQ_MACH_EASY336)*/
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+ 1) {
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+ /* We just use the CPLD function to reset the entire system as a
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+ workaround for the switch reset problem */
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+ local_irq_disable();
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+ ltq_ebu_w32(0x120000f1, LTQ_EBU_ADDRSEL2);
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+ ltq_ebu_w32(0x404027ff, LTQ_EBU_BUSCON2);
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+
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+ if (/*mips_machtype == LANTIQ_MACH_EASY336*/
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+ 0)
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+ /* set bit 0 to reset SVIP */
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+ *CPLD_CMDREG3 = (1<<0);
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+ else
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+ /* set bit 7 to reset SVIP, set bit 3 to reset xT */
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+ *CPLD_CMDREG3 = (1<<7) | (1<<3);
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+ } else {
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+ *LTQ_BOOT_RVEC(0) = 0;
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+ /* reset all except PER, SUBSYS and CPU0 */
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+ ltq_sys1_w32(0x00043F3E, SYS1_RREQR);
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+ /* release WDT0 reset */
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+ ltq_sys1_w32(0x00000100, SYS1_RRLSR);
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+ /* restore reset value for clock enables */
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+ ltq_sys1_w32(~0x0c000040, SYS1_CLKCLR);
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+ /* reset SUBSYS (incl. DDR2) and CPU0 */
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+ ltq_sys1_w32(0x00030001, SYS1_RBTR);
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+ }
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+
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+ unreachable();
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+}
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+
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+static void ltq_machine_halt(void)
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+{
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+ local_irq_disable();
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+ unreachable();
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+}
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+
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+static void ltq_machine_power_off(void)
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+{
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+ local_irq_disable();
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+}
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+
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+static int __init mips_reboot_setup(void)
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+{
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+ _machine_restart = ltq_machine_restart;
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+ _machine_halt = ltq_machine_halt;
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+ pm_power_off = ltq_machine_power_off;
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+ return 0;
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+}
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+
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+arch_initcall(mips_reboot_setup);
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--- /dev/null
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+++ b/arch/mips/lantiq/svip/sysctrl.c
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@@ -0,0 +1,81 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2011-2012 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/ioport.h>
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+#include <linux/export.h>
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+#include <linux/clkdev.h>
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+#include <linux/of.h>
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+#include <linux/of_platform.h>
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+#include <linux/of_address.h>
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+
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+#include <lantiq_soc.h>
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+
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+#include "../clk.h"
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+#include "../prom.h"
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+
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+void __iomem *ltq_sys0_membase;
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+void __iomem *ltq_sys1_membase;
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+void __iomem *ltq_sys2_membase;
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+void __iomem *ltq_status_membase;
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+void __iomem *ltq_ebu_membase;
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+
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+/* bring up all register ranges that we need for basic system control */
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+void __init ltq_soc_init(void)
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+{
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+ struct resource res_sys0, res_sys1, res_sys2, res_status, res_ebu;
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+ struct device_node *np_sys0 =
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+ of_find_compatible_node(NULL, NULL, "lantiq,sys0-svip");
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+ struct device_node *np_sys1 =
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+ of_find_compatible_node(NULL, NULL, "lantiq,sys1-svip");
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+ struct device_node *np_sys2 =
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+ of_find_compatible_node(NULL, NULL, "lantiq,sys2-svip");
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+ struct device_node *np_status =
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+ of_find_compatible_node(NULL, NULL, "lantiq,status-svip");
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+ struct device_node *np_ebu =
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+ of_find_compatible_node(NULL, NULL, "lantiq,ebu-svip");
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+
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+ /* check if all the core register ranges are available */
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+ if (!np_sys0 || !np_sys1 || !np_sys2 || !np_status || !np_ebu)
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+ panic("Failed to load core nodes from devicetree");
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+
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+ if (of_address_to_resource(np_sys0, 0, &res_sys0) ||
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+ of_address_to_resource(np_sys1, 0, &res_sys1) ||
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+ of_address_to_resource(np_sys2, 0, &res_sys2) ||
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+ of_address_to_resource(np_status, 0, &res_status) ||
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+ of_address_to_resource(np_ebu, 0, &res_ebu))
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+ panic("Failed to get core resources");
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+
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+ if ((request_mem_region(res_sys0.start, resource_size(&res_sys0),
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+ res_sys0.name) < 0) ||
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+ (request_mem_region(res_sys1.start, resource_size(&res_sys1),
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+ res_sys1.name) < 0) ||
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+ (request_mem_region(res_sys2.start, resource_size(&res_sys2),
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+ res_sys2.name) < 0) ||
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+ (request_mem_region(res_status.start, resource_size(&res_status),
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+ res_status.name) < 0) ||
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+ (request_mem_region(res_ebu.start, resource_size(&res_ebu),
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+ res_ebu.name) < 0))
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+ pr_err("Failed to request core reources");
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+
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+ ltq_sys0_membase = ioremap_nocache(res_sys0.start,
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+ resource_size(&res_sys0));
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+ ltq_sys1_membase = ioremap_nocache(res_sys1.start,
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+ resource_size(&res_sys1));
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+ ltq_sys2_membase = ioremap_nocache(res_sys2.start,
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+ resource_size(&res_sys2));
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+ ltq_status_membase = ioremap_nocache(res_status.start,
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+ resource_size(&res_status));
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+ ltq_ebu_membase = ioremap_nocache(res_ebu.start,
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+ resource_size(&res_ebu));
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+ if (!ltq_sys0_membase || !ltq_sys1_membase || !ltq_sys2_membase ||
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+ !ltq_status_membase || !ltq_ebu_membase)
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+ panic("Failed to remap core resources");
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+
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+ clkdev_add_static(ltq_svip_cpu_hz(), ltq_svip_fpi_hz(),
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+ ltq_svip_io_hz());
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+}
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