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406 lines
15 KiB
Diff
406 lines
15 KiB
Diff
--- /dev/null
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+++ b/drivers/net/arm/ep93xx_eth.h
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@@ -0,0 +1,402 @@
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+/*------------------------------------------------------------------------
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+ * ep93xx_eth.h
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+ * : header file of Ethernet Device Driver for Cirrus Logic EP93xx.
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+ *
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+ * Copyright (C) 2003 by Cirrus Logic www.cirrus.com
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+ * This software may be used and distributed according to the terms
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+ * of the GNU Public License.
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+ *
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+ * This file contains device related information like register info
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+ * and register access method macros for the Ethernet device
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+ * embedded within Cirrus Logic's EP93xx SOC chip.
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+ *
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+ * Information contained in this file was obtained from
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+ * the EP9312 Manual Revision 0.12 and 0.14 from Cirrus Logic.
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+ *
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+ * History
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+ * 05/18/01 Sungwook Kim Initial release
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+ * 03/25/2003 Melody Modified for EP92xx
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+ *--------------------------------------------------------------------------*/
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+
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+
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+#ifndef _EP9213_ETH_H_
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+#define _EP9213_ETH_H_
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+
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+
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+/*---------------------------------------------------------------
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+ * Definition of H/W Defects and Their Workarounds
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+ *-------------------------------------------------------------*/
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+
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+
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+
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+/*---------------------------------------------------------------
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+ * Data types used in this driver
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+ *-------------------------------------------------------------*/
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+typedef unsigned char U8;
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+typedef unsigned short U16;
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+typedef unsigned long U32;
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+typedef unsigned int UINT;
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+
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+
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+
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+/*---------------------------------------------------------------
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+ * Definition of the registers.
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+ * For details, refer to the datasheet .
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+ *
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+ * Basically, most registers are 32 bits width register.
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+ * But some are 16 bits and some are 6 or 8 bytes long.
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+ *-------------------------------------------------------------*/
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+
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+#define REG_RxCTL 0x0000 /*offset to Receiver Control Reg*/
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+#define RxCTL_PauseA (1<<20)
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+#define RxCTL_RxFCE1 (1<<19)
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+#define RxCTL_RxFCE0 (1<<18)
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+#define RxCTL_BCRC (1<<17)
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+#define RxCTL_SRxON (1<<16)
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+#define RxCTL_RCRCA (1<<13)
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+#define RxCTL_RA (1<<12)
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+#define RxCTL_PA (1<<11)
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+#define RxCTL_BA (1<<10)
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+#define RxCTL_MA (1<<9)
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+#define RxCTL_IAHA (1<<8)
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+#define RxCTL_IA3 (1<<3)
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+#define RxCTL_IA2 (1<<2)
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+#define RxCTL_IA1 (1<<1)
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+#define RxCTL_IA0 (1<<0)
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+
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+#define REG_TxCTL 0x0004 /*offset to Transmit Control Reg*/
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+#define TxCTL_DefDis (1<<7)
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+#define TxCTL_MBE (1<<6)
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+#define TxCTL_ICRC (1<<5)
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+#define TxCTL_TxPD (1<<5)
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+#define TxCTL_OColl (1<<3)
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+#define TxCTL_SP (1<<2)
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+#define TxCTL_PB (1<<1)
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+#define TxCTL_STxON (1<<0)
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+
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+#define REG_TestCTL 0x0008 /*Test Control Reg, R/W*/
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+#define TestCTL_MACF (1<<7)
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+#define TestCTL_MFDX (1<<6)
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+#define TestCTL_DB (1<<5)
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+#define TestCTL_MIIF (1<<4)
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+
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+#define REG_MIICmd 0x0010 /*offset to MII Command Reg, R/W*/
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+#define MIICmd_OP (0x03<<14)
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+#define MIICmd_OP_RD (2<<14)
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+#define MIICmd_OP_WR (1<<14)
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+#define MIICmd_PHYAD (0x1f<<5)
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+#define MIICmd_REGAD (0x1f<<0)
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+
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+#define REG_MIIData 0x0014 /*offset to MII Data Reg, R/W*/
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+#define MIIData_MIIData (0xffff<<0)
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+
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+#define REG_MIISts 0x0018 /*offset to MII Status Reg, R*/
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+#define MIISts_Busy (1<<0)
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+
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+#define REG_SelfCTL 0x0020 /*offset to Self Control Reg*/
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+#define SelfCTL_RWP (1<<7) /*Remote Wake Pin*/
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+#define SelfCTL_GPO0 (1<<5)
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+#define SelfCTL_PUWE (1<<4)
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+#define SelfCTL_PDWE (1<<3)
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+#define SelfCTL_MIIL (1<<2)
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+#define SelfCTL_RESET (1<<0)
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+
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+#define REG_IntEn 0x0024 /*Interrupt Enable Reg, R/W*/
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+#define IntEn_RWIE (1<<30)
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+#define IntEn_RxMIE (1<<29)
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+#define IntEn_RxBIE (1<<28)
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+#define IntEn_RxSQIE (1<<27)
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+#define IntEn_TxLEIE (1<<26)
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+#define IntEn_ECIE (1<<25)
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+#define IntEn_TxUHIE (1<<24)
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+#define IntEn_MOIE (1<<18)
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+#define IntEn_TxCOIE (1<<17)
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+#define IntEn_RxROIE (1<<16)
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+#define IntEn_MIIIE (1<<12)
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+#define IntEn_PHYSIE (1<<11)
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+#define IntEn_TIE (1<<10)
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+#define IntEn_SWIE (1<<8)
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+#define IntEn_TxSQIE (1<<3)
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+#define IntEn_RxEOFIE (1<<2)
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+#define IntEn_RxEOBIE (1<<1)
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+#define IntEn_RxHDRIE (1<<0)
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+
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+#define REG_IntStsP 0x0028 /*offset to Interrupt Status Preserve Reg, R/W*/
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+#define REG_IntStsC 0x002c /*offset to Interrupt Status Clear Reg, R*/
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+#define IntSts_RWI (1<<30)
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+#define IntSts_RxMI (1<<29)
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+#define IntSts_RxBI (1<<28)
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+#define IntSts_RxSQI (1<<27)
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+#define IntSts_TxLEI (1<<26)
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+#define IntSts_ECI (1<<25)
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+#define IntSts_TxUHI (1<<24)
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+#define IntSts_MOI (1<<18)
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+#define IntSts_TxCOI (1<<17)
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+#define IntSts_RxROI (1<<16)
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+#define IntSts_MIII (1<<12)
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+#define IntSts_PHYSI (1<<11)
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+#define IntSts_TI (1<<10)
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+#define IntSts_AHBE (1<<9)
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+#define IntSts_SWI (1<<8)
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+#define IntSts_OTHER (1<<4)
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+#define IntSts_TxSQ (1<<3)
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+#define IntSts_RxSQ (1<<2)
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+
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+#define REG_GT 0x0040 /*offset to General Timer Reg*/
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+#define GT_GTC (0xffff<<16)
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+#define GT_GTP (0xffff<<0)
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+
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+#define REG_FCT 0x0044 /*offset to Flow Control Timer Reg*/
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+#define FCT_FCT (0x00ffffff<<0)
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+
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+#define REG_FCF 0x0048 /*offset to Flow Control Format Reg*/
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+#define FCF_MACCT (0xffff<<16)
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+#define FCF_TPT (0xffff<<0)
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+
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+#define REG_AFP 0x004c /*offset to Address Filter Pointer Reg*/
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+#define AFP_AFP (0x07<<0) /*Address Filter Pointer (bank control for REG_IndAD)*/
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+#define AFP_AFP_IA0 0 /*Primary Individual Address (MAC Addr)*/
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+#define AFP_AFP_IA1 1 /*Individual Address 1*/
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+#define AFP_AFP_IA2 2 /*Individual Address 2*/
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+#define AFP_AFP_IA3 3 /*Individual Address 3*/
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+#define AFP_AFP_DTxP 6 /*Destination Address of Tx Pause Frame*/
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+#define AFP_AFP_HASH 7 /*Hash Table*/
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+
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+#define REG_IndAD 0x0050 /*offset to Individual Address Reg, n bytes, R/W*/
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+
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+#define REG_GIntSts 0x0060 /*offset to Global Interrupt Status Reg (writing 1 will clear)*/
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+#define REG_GIntROS 0x0068 /*offset to Global Interrupt Status Read Only Reg*/
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+#define GIntSts_INT (1<<15) /*Global Interrupt Request Status*/
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+
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+#define REG_GIntMsk 0x0064 /*offset to Global Interrupt Mask Reg*/
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+#define GIntMsk_IntEn (1<<15) /*Global Interrupt Enable*/
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+
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+#define REG_GIntFrc 0x006c /*offset to Global Interrupt Force Reg*/
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+#define GIntFrc_INT (1<<15) /*Force to set GIntSts*/
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+
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+#define REG_TxCollCnt 0x0070 /*Transmit Collision Count Reg, R*/
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+#define REG_RxMissCnt 0x0074 /*Receive Miss Count Reg, R*/
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+#define REG_RxRntCnt 0x0078 /*Receive Runt Count Reg, R*/
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+
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+#define REG_BMCtl 0x0080 /*offset to Bus Master Control Reg, R/W*/
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+#define BMCtl_MT (1<<13)
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+#define BMCtl_TT (1<<12)
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+#define BMCtl_UnH (1<<11)
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+#define BMCtl_TxChR (1<<10)
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+#define BMCtl_TxDis (1<<9)
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+#define BMCtl_TxEn (1<<8)
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+#define BMCtl_EH2 (1<<6)
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+#define BMCtl_EH1 (1<<5)
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+#define BMCtl_EEOB (1<<4)
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+#define BMCtl_RxChR (1<<2)
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+#define BMCtl_RxDis (1<<1)
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+#define BMCtl_RxEn (1<<0)
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+
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+#define REG_BMSts 0x0084 /*offset to Bus Master Status Reg, R*/
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+#define BMSts_TxAct (1<<7)
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+#define BMSts_TP (1<<4)
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+#define BMSts_RxAct (1<<3)
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+#define BMSts_QID (0x07<<0)
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+#define BMSts_QID_RxDt (0<<0)
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+#define BMSts_QID_TxDt (1<<0)
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+#define BMSts_QID_RxSts (2<<0)
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+#define BMSts_QID_TxSts (3<<0)
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+#define BMSts_QID_RxDesc (4<<0)
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+#define BMSts_QID_TxDesc (5<<0)
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+
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+#define REG_RBCA 0x0088 /*offset to Receive Buffer Current Address Reg, R*/
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+#define REG_TBCA 0x008c /*offset to Transmit Buffer Current Address Reg, R*/
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+
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+#define REG_RxDBA 0x0090 /*offset to Receive Descriptor Queue Base Address Reg, R/W*/
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+#define REG_RxDBL 0x0094 /*offset to Receive Descriptor Queue Base Length Reg, R/W, 16bits*/
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+#define REG_RxDCL 0x0096 /*offset to Receive Descriptor Queue Current Length Reg, R/W, 16bits*/
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+#define REG_RxDCA 0x0098 /*offset to Receive Descriptor Queue Current Address Reg, R/W*/
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+
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+#define REG_RxDEQ 0x009c /*offset to Receive Descriptor Enqueue Reg, R/W*/
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+#define RxDEQ_RDV (0xffff<<16) /*R 16bit; Receive Descriptor Value*/
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+#define RxDEQ_RDI (0xff<<0) /*W 8bit; Receive Descriptor Increment*/
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+
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+#define REG_RxSBA 0x00a0 /*offset to Receive Status Queue Base Address Reg, R/W*/
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+#define REG_RxSBL 0x00a4 /*offset to Receive Status Queue Base Length Reg, R/W, 16bits*/
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+#define REG_RxSCL 0x00a6 /*offset to Receive Status Queue Current Length Reg, R/W, 16bits*/
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+#define REG_RxSCA 0x00a8 /*offset to Receive Status Queue Current Address Reg, R/W*/
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+
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+#define REG_RxSEQ 0x00ac /*offset to Receive Status Queue Current Address Reg, R/W*/
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+#define RxSEQ_RSV (0xffff<<16)
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+#define RxSEQ_RSI (0xff<<0)
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+
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+#define REG_TxDBA 0x00b0 /*offset to Transmit Descriptor Queue Base Address Reg, R/W*/
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+#define REG_TxDBL 0x00b4 /*offset to Transmit Descriptor Queue Base Length Reg, R/W, 16bits*/
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+#define REG_TxDCL 0x00b6 /*offset to Transmit Descriptor Queue Current Length Reg, R/W, 16bits*/
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+#define REG_TxDCA 0x00b8 /*offset to Transmit Descriptor Queue Current Address Reg, R/W*/
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+
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+#define REG_TxDEQ 0x00bc /*offset to Transmit Descriptor Queue Current Address Reg, R/W*/
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+#define TxDEQ_TDV (0xffff<<16)
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+#define TxDEQ_TDI (0xff<<0)
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+
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+#define REG_TxSBA 0x00c0 /*offset to Transmit Status Queue Base Address Reg, R/W*/
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+#define REG_TxSBL 0x00c4 /*offset to Transmit Status Queue Base Length Reg, R/W, 16bits*/
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+#define REG_TxSCL 0x00c6 /*offset to Transmit Status Queue Current Length Reg, R/W, 16bits*/
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+#define REG_TxSCA 0x00c8 /*offset to Transmit Status Queue Current Address Reg, R/W*/
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+
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+#define REG_RxBTH 0x00d0 /*offset to Receive Buffer Threshold Reg, R/W*/
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+#define RxBTH_RDHT (0x03ff<<16)
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+#define RxBTH_RDST (0x03ff<<0)
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+
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+#define REG_TxBTH 0x00d4 /*offset to Transmit Buffer Threshold Reg, R/W*/
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+#define TxBTH_TDHT (0x03ff<<16)
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+#define TxBTH_TDST (0x03ff<<0)
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+
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+#define REG_RxSTH 0x00d8 /*offset to Receive Status Threshold Reg, R/W*/
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+#define RxSTH_RSHT (0x003f<<16)
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+#define RxSTH_RSST (0x003f<<0)
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+
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+#define REG_TxSTH 0x00dc /*offset to Transmit Status Threshold Reg, R/W*/
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+#define TxSTH_TSHT (0x003f<<16)
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+#define TxSTH_TSST (0x003f<<0)
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+
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+#define REG_RxDTH 0x00e0 /*offset to Receive Descriptor Threshold Reg, R/W*/
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+#define RxDTH_RDHT (0x003f<<16)
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+#define RxDTH_RDST (0x003f<<0)
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+
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+#define REG_TxDTH 0x00e4 /*offset to Transmit Descriptor Threshold Reg, R/W*/
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+#define TxDTH_TDHT (0x003f<<16)
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+#define TxDTH_TDST (0x003f<<0)
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+
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+#define REG_MaxFL 0x00e8 /*offset to Max Frame Length Reg, R/W*/
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+#define MaxFL_MFL (0x07ff<<16)
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+#define MaxFL_TST (0x07ff<<0)
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+
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+#define REG_RxHL 0x00ec /*offset to Receive Header Length Reg, R/W*/
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+#define RxHL_RHL2 (0x07ff<<16)
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+#define RxHL_RHL1 (0x03ff<<0)
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+
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+#define REG_MACCFG0 0x0100 /*offset to Test Reg #0, R/W*/
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+#define MACCFG0_DbgSel (1<<7)
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+#define MACCFG0_LCKEN (1<<6)
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+#define MACCFG0_LRATE (1<<5)
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+#define MACCFG0_RXERR (1<<4)
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+#define MACCFG0_BIT33 (1<<2)
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+#define MACCFG0_PMEEN (1<<1)
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+#define MACCFG0_PMEST (1<<0)
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+
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+#define REG_MACCFG1 0x0104 /*offset to Test Reg #1, R/W*/
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+#define REG_MACCFG2 0x0108 /*offset to Test Reg #2, R*/
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+#define REG_MACCFG3 0x010c /*offset to Test Reg #3, R*/
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+
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+
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+
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+/*---------------------------------------------------------------
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+ * Definition of Descriptor/Status Queue Entry
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+ *-------------------------------------------------------------*/
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+
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+typedef union receiveDescriptor { /*data structure of Receive Descriptor Queue Entry*/
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+ struct { /*whole value*/
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+ U32 e0, /*1st dword entry*/
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+ e1; /*2nd dword entry*/
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+ } w;
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+ struct { /*bit field definitions*/
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+ U32 ba:32, /*Buffer Address (keep in mind this is physical address)*/
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+ bl:16, /*b15-0; Buffer Length*/
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+ bi:15, /*b30-16; Buffer Index*/
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+ nsof:1; /*b31; Not Start Of Frame*/
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+ } f;
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+} receiveDescriptor;
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+
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+
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+typedef union receiveStatus { /*data structure of Receive Status Queue Entry*/
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+ struct { /*whole word*/
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+ U32 e0, /*1st dword entry*/
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+ e1; /*2nd dword entry*/
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+ } w;
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+ struct { /*bit field*/
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+ U32 rsrv1:8, /*b7-0: reserved*/
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+ hti:6, /*b13-8: Hash Table Index*/
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+ rsrv2:1, /*b14: reserved*/
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+ crci:1, /*b15: CRC Included*/
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+ crce:1, /*b16: CRC Error*/
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+ edata:1, /*b17: Extra Data*/
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+ runt:1, /*b18: Runt Frame*/
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+ fe:1, /*b19: Framing Error*/
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+ oe:1, /*b20: Overrun Error*/
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+ rxerr:1, /*b21: Rx Error*/
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+ am:2, /*b23-22: Address Match*/
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+ rsrv3:4, /*b27-24: reserved*/
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+ eob:1, /*b28: End Of Buffer*/
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+ eof:1, /*b29: End Of Frame*/
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+ rwe:1, /*b30: Received Without Error*/
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+ rfp:1, /*b31: Receive Frame Processed*/
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+ fl:16, /*b15-0: frame length*/
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+ bi:15, /*b30-16: Buffer Index*/
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+ rfp2:1; /*b31: Receive Frame Processed at 2nd word*/
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+ } f;
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+} receiveStatus;
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+
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+
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+typedef union transmitDescriptor { /*data structure of Transmit Descriptor Queue Entry*/
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+ struct { /*whole value*/
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+ U32 e0, /*1st dword entry*/
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+ e1; /*2nd dword entry*/
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+ } w;
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+ struct { /*bit field*/
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+ U32 ba:32, /*b31-0: Buffer Address (keep in mind this is physical address)*/
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+ bl:12, /*b11-0: Buffer Length*/
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+ rsrv1:3, /*b14-12: reserved*/
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+ af:1, /*b15: Abort Frame*/
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+ bi:15, /*b30-16: Buffer Index*/
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+ eof:1; /*b31: End Of Frame*/
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+
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+ } f;
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+} transmitDescriptor;
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+
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+
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+typedef union transmitStatus { /*data structure of Transmit Status Queue Entry*/
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+ struct { /*whole word*/
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+ U32 e0; /*1st dword entry*/
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+ } w;
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+ struct { /*bit field*/
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+ U32 bi:15, /*b14-0: Buffer Index*/
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+ rsrv3:1, /*b15: reserved*/
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+ ncoll:5, /*b20-16: Number of Collisions*/
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+ rsrv2:3, /*b23-21: reserved*/
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+ ecoll:1, /*b24: Excess Collisions*/
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+ txu:1, /*b25: Tx Underrun*/
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+ ow:1, /*b26: Out of Window*/
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+ rsrv1:1, /*b27: reserved*/
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+ lcrs:1, /*b28: Loss of CRS*/
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+ fa:1, /*b29: Frame Abort*/
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+ txwe:1, /*b30: Transmitted Without Error*/
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+ txfp:1; /*b31: Transmit Frame Processed*/
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+ } f;
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+} transmitStatus;
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+
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+
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+
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+/*---------------------------------------------------------------
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+ * Size of device registers occupied in memory/IO address map
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+ *-------------------------------------------------------------*/
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+#define DEV_REG_SPACE 0x00010000
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+
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+/*
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+#define U8 unsigned char
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+#define U16 unsigned short
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+#define U32 unsigned long
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+*/
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+
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+/*---------------------------------------------------------------
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+ * A definition of register access macros
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+ *-------------------------------------------------------------*/
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+#define _RegRd(type,ofs) (*(volatile type*)(ofs))
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+#define _RegWr(type,ofs,dt) *(volatile type*)(ofs)=((type)(dt))
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+
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+#define RegRd8(ofs) _RegRd(U8,(char*)pD->base_addr+(ofs))
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+#define RegRd16(ofs) _RegRd(U16,(char*)pD->base_addr+(ofs))
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+#define RegRd32(ofs) _RegRd(U32,(char*)pD->base_addr+(ofs))
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+#define RegWr8(ofs,dt) _RegWr(U8,(char*)pD->base_addr+(ofs),(dt))
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+#define RegWr16(ofs,dt) _RegWr(U16,(char*)pD->base_addr+(ofs),(dt))
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+#define RegWr32(ofs,dt) _RegWr(U32,(char*)pD->base_addr+(ofs),(dt))
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+
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+
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+
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+#endif /* _EP9213_ETH_H_ */
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+
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