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711 lines
18 KiB
Diff
711 lines
18 KiB
Diff
--- a/drivers/mtd/nand/Kconfig
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+++ b/drivers/mtd/nand/Kconfig
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@@ -536,4 +536,12 @@ config MTD_NAND_FSMC
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Enables support for NAND Flash chips on the ST Microelectronics
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Flexible Static Memory Controller (FSMC)
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+config MTD_NAND_BCM47XX
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+ tristate "bcm47xx nand flash support"
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+ default y
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+ depends on BCM47XX && BCMA_NFLASH
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+ select MTD_PARTITIONS
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+ help
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+ Support for bcm47xx nand flash
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+
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endif # MTD_NAND
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--- a/drivers/mtd/nand/Makefile
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+++ b/drivers/mtd/nand/Makefile
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@@ -49,5 +49,6 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mp
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obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
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obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
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obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
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+obj-$(CONFIG_MTD_NAND_BCM47XX) += bcm47xx_nand.o
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nand-objs := nand_base.o nand_bbt.o
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--- /dev/null
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+++ b/drivers/mtd/nand/bcm47xx_nand.c
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@@ -0,0 +1,528 @@
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+/*
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+ * BCMA nand flash interface
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+ *
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+ * Copyright (C) 2011-2012 Tathagata Das <tathagata@alumnux.com>
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+ * Copyright 2010, Broadcom Corporation
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+ *
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+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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+ *
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+ */
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+
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+#define pr_fmt(fmt) "bcm47xx_nflash: " fmt
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+#include <linux/module.h>
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+#include <linux/slab.h>
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+#include <linux/ioport.h>
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+#include <linux/sched.h>
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/map.h>
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+#include <linux/mtd/partitions.h>
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+#include <linux/errno.h>
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+#include <linux/delay.h>
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+#include <linux/platform_device.h>
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+#include <bcm47xx.h>
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+#include <linux/cramfs_fs.h>
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+#include <linux/romfs_fs.h>
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+#include <linux/magic.h>
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+#include <linux/byteorder/generic.h>
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+#include <linux/mtd/bcm47xx_nand.h>
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+#include <linux/mtd/nand.h>
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+
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+static int bcm47xx_nflash_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip);
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+static int bcm47xx_nflash_erase(struct mtd_info *mtd, unsigned int addr, unsigned int len);
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+
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+/* Private Global variable */
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+static u32 read_offset = 0;
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+static u32 write_offset;
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+
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+static int
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+nflash_mtd_poll(struct bcm47xx_nflash *nflash, unsigned int offset, int timeout)
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+{
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+ unsigned long now = jiffies;
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+ int ret = 0;
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+
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+ for (;;) {
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+ if (!bcma_nflash_poll(nflash->bcc)) {
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+ ret = 0;
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+ break;
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+ }
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+ if (time_after(jiffies, now + timeout)) {
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+ pr_err("timeout while polling\n");
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+ ret = -ETIMEDOUT;
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+ break;
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+ }
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+ udelay(1);
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+ }
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+
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+ return ret;
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+}
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+
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+static int
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+bcm47xx_nflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
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+{
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+ struct nand_chip *nchip = (struct nand_chip *)mtd->priv;
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+ struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
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+ int bytes, ret = 0;
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+ u32 extra = 0;
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+ u8 *tmpbuf = NULL;
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+ int size;
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+ u32 offset, blocksize, mask, off;
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+ u32 skip_bytes = 0;
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+ int need_copy = 0;
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+ u8 *ptr = NULL;
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+
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+ /* Check address range */
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+ if (!len)
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+ return 0;
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+ if ((from + len) > mtd->size)
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+ return -EINVAL;
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+ offset = from;
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+ if ((offset & (NFL_SECTOR_SIZE - 1)) != 0) {
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+ extra = offset & (NFL_SECTOR_SIZE - 1);
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+ offset -= extra;
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+ len += extra;
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+ need_copy = 1;
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+ }
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+ size = (len + (NFL_SECTOR_SIZE - 1)) & ~(NFL_SECTOR_SIZE - 1);
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+ if (size != len) {
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+ need_copy = 1;
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+ }
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+ if (!need_copy) {
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+ ptr = buf;
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+ } else {
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+ tmpbuf = (u8 *)kmalloc(size, GFP_KERNEL);
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+ ptr = tmpbuf;
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+ }
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+
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+ blocksize = mtd->erasesize;
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+ mask = blocksize - 1;
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+ *retlen = 0;
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+ while (len > 0) {
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+ off = offset + skip_bytes;
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+ if ((bytes = bcma_nflash_read(nflash->bcc, off, NFL_SECTOR_SIZE, ptr)) < 0) {
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+ ret = bytes;
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+ goto done;
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+ }
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+ if (bytes > len)
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+ bytes = len;
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+ offset += bytes;
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+ len -= bytes;
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+ ptr += bytes;
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+ *retlen += bytes;
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+ }
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+
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+done:
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+ if (tmpbuf) {
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+ *retlen -= extra;
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+ memcpy(buf, tmpbuf+extra, *retlen);
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+ kfree(tmpbuf);
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+ }
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+
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+ return ret;
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+}
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+
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+static void bcm47xx_nflash_write(struct mtd_info *mtd, u32 to, const u_char *buf, u32 len)
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+{
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+ struct nand_chip *nchip = (struct nand_chip *)mtd->priv;
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+ struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
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+ u32 offset, blocksize, mask, off;
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+ int read_len;
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+ u32 copy_len, write_len, from;
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+ u_char *write_ptr, *block;
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+ const u_char *ptr;
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+ int ret, bytes;
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+
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+ /* Check address range */
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+ if (!len) {
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+ pr_err("Error: Attempted to write too small data\n");
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+ return;
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+ }
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+
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+ if (!to)
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+ return;
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+
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+ if ((to + len) > mtd->size) {
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+ pr_err("Error: Attempted to write too large data\n");
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+ return;
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+ }
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+
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+ ptr = buf;
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+ block = NULL;
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+ offset = to;
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+ blocksize = mtd->erasesize;
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+ if (!(block = kmalloc(blocksize, GFP_KERNEL)))
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+ return;
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+ mask = blocksize - 1;
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+ while (len) {
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+ /* Align offset */
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+ from = offset & ~mask;
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+ /* Copy existing data into holding block if necessary */
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+ if (((offset & (blocksize-1)) != 0) || (len < blocksize)) {
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+ if ((ret = bcm47xx_nflash_read(mtd, from, blocksize, &read_len, block)))
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+ goto done;
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+ if (read_len != blocksize) {
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+ ret = -EINVAL;
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+ goto done;
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+ }
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+ }
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+
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+ /* Copy input data into holding block */
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+ copy_len = min(len, blocksize - (offset & mask));
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+ memcpy(block + (offset & mask), ptr, copy_len);
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+ off = (uint) from;
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+ /* Erase block */
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+ if ((ret = bcm47xx_nflash_erase(mtd, off, blocksize)) < 0)
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+ goto done;
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+ /* Write holding block */
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+ write_ptr = block;
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+ write_len = blocksize;
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+ if ((bytes = bcma_nflash_write(nflash->bcc, (uint)from, (uint)write_len, (u8 *) write_ptr)) != 0) {
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+ ret = bytes;
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+ goto done;
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+ }
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+ offset += copy_len;
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+ if (len < copy_len)
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+ len = 0;
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+ else
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+ len -= copy_len;
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+ ptr += copy_len;
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+ }
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+
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+done:
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+ if (block)
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+ kfree(block);
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+ return;
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+}
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+
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+static int bcm47xx_nflash_erase(struct mtd_info *mtd, unsigned int addr, unsigned int len)
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+{
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+ struct nand_chip *nchip = (struct nand_chip *)mtd->priv;
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+ struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
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+
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+ /* Check address range */
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+ if (!len)
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+ return 1;
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+ if ((addr + len) > mtd->size)
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+ return 1;
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+
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+ if (bcma_nflash_erase(nflash->bcc, addr)) {
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+ pr_err("ERASE: nflash erase error\n");
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+ return 1;
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+ }
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+
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+ if (nflash_mtd_poll(nflash, addr, 10 * HZ)) {
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+ pr_err("ERASE: nflash_mtd_poll error\n");
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+ return 1;
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+ }
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+
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+ return 0;
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+}
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+
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+/* This functions is used by upper layer to checks if device is ready */
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+static int bcm47xx_nflash_dev_ready(struct mtd_info *mtd)
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+{
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+ return 1;
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+}
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+
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+/* Issue a nand flash command */
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+static inline void bcm47xx_nflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
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+{
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+ bcma_cc_write32(cc, NAND_CMD_START, opcode);
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+ bcma_cc_read32(cc, NAND_CMD_START);
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+}
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+
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+static void bcm47xx_nflash_command(struct mtd_info *mtd, unsigned command,
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+ int column, int page_addr)
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+{
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+ struct nand_chip *nchip = (struct nand_chip *)mtd->priv;
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+ struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
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+ u32 pagesize = 1 << nchip->page_shift;
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+
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+ /* Command pre-processing step */
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+ switch (command) {
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+ case NAND_CMD_RESET:
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+ bcm47xx_nflash_cmd(nflash->bcc, NCMD_FLASH_RESET);
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+ break;
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+
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+ case NAND_CMD_STATUS:
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+ nflash->next_opcode = NAND_CMD_STATUS;
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+ read_offset = 0;
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+ write_offset = 0;
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+ break;
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+
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+ case NAND_CMD_READ0:
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+ read_offset = page_addr * pagesize;
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+ nflash->next_opcode = 0;
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+ break;
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+
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+ case NAND_CMD_READOOB:
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+ read_offset = page_addr * pagesize;
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+ nflash->next_opcode = 0;
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+ break;
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+
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+ case NAND_CMD_SEQIN:
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+ write_offset = page_addr * pagesize;
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+ nflash->next_opcode = 0;
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+ break;
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+
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+ case NAND_CMD_PAGEPROG:
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+ nflash->next_opcode = 0;
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+ break;
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+
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+ case NAND_CMD_READID:
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+ read_offset = column;
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+ bcm47xx_nflash_cmd(nflash->bcc, NCMD_ID_RD);
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+ nflash->next_opcode = NAND_DEVID;
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+ break;
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+
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+ case NAND_CMD_ERASE1:
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+ nflash->next_opcode = 0;
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+ bcm47xx_nflash_erase(mtd, page_addr*pagesize, pagesize);
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+ break;
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+
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+ case NAND_CMD_ERASE2:
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+ break;
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+
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+ case NAND_CMD_RNDOUT:
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+ if (column > mtd->writesize)
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+ read_offset += (column - mtd->writesize);
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+ else
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+ read_offset += column;
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+ break;
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+
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+ default:
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+ pr_err("COMMAND not supported %x\n", command);
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+ nflash->next_opcode = 0;
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+ break;
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+ }
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+}
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+
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+/* This function is used by upper layer for select and
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+ * deselect of the NAND chip.
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+ * It is dummy function. */
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+static void bcm47xx_nflash_select_chip(struct mtd_info *mtd, int chip)
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+{
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+}
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+
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+static u_char bcm47xx_nflash_read_byte(struct mtd_info *mtd)
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+{
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+ struct nand_chip *nchip = mtd->priv;
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+ struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
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+ uint8_t ret = 0;
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+ static u32 id;
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+
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+ if (nflash->next_opcode == 0)
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+ return ret;
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+
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+ if (nflash->next_opcode == NAND_CMD_STATUS)
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+ return NAND_STATUS_WP;
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+
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+ id = bcma_cc_read32(nflash->bcc, nflash->next_opcode);
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+
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+ if (nflash->next_opcode == NAND_DEVID) {
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+ ret = (id >> (8*read_offset)) & 0xff;
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+ read_offset++;
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+ }
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+
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+ return ret;
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+}
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+
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+static uint16_t bcm47xx_nflash_read_word(struct mtd_info *mtd)
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+{
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+ loff_t from = read_offset;
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+ uint16_t buf = 0;
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+ int bytes;
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+
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+ bcm47xx_nflash_read(mtd, from, sizeof(buf), &bytes, (u_char *)&buf);
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+ return buf;
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+}
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+
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+/* Write data of length len to buffer buf. The data to be
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+ * written on NAND Flash is first copied to RAMbuffer. After the Data Input
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+ * Operation by the NFC, the data is written to NAND Flash */
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+static void bcm47xx_nflash_write_buf(struct mtd_info *mtd,
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+ const u_char *buf, int len)
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+{
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+ bcm47xx_nflash_write(mtd, write_offset, buf, len);
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+}
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+
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+/* Read the data buffer from the NAND Flash. To read the data from NAND
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+ * Flash first the data output cycle is initiated by the NFC, which copies
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+ * the data to RAMbuffer. This data of length len is then copied to buffer buf.
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+ */
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+static void bcm47xx_nflash_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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+{
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+ loff_t from = read_offset;
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+ int bytes;
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+
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+ bcm47xx_nflash_read(mtd, from, len, &bytes, buf);
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+}
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+
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+/* Used by the upper layer to verify the data in NAND Flash
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+ * with the data in the buf. */
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+static int bcm47xx_nflash_verify_buf(struct mtd_info *mtd,
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+ const u_char *buf, int len)
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+{
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+ return -EFAULT;
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+}
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+
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+static int bcm47xx_nflash_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
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+{
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+ struct nand_chip *nchip = mtd->priv;
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+ struct bcm47xx_nflash *nflash = (struct bcm47xx_nflash *)nchip->priv;
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+ int i;
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+ uint off;
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+ u32 pagesize = 1 << nchip->page_shift;
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+ u32 blocksize = mtd->erasesize;
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+
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+ if ((ofs >> 20) >= nflash->size)
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+ return 1;
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+ if ((ofs & (blocksize - 1)) != 0)
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+ return 1;
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+
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+ for (i = 0; i < 2; i++) {
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+ off = ofs + pagesize;
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+ bcma_cc_write32(nflash->bcc, NAND_CMD_ADDR, off);
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+ bcm47xx_nflash_cmd(nflash->bcc, NCMD_SPARE_RD);
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+ if (bcma_nflash_poll(nflash->bcc) < 0)
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+ break;
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+ if ((bcma_cc_read32(nflash->bcc, NAND_INTFC_STATUS) & NIST_SPARE_VALID) != NIST_SPARE_VALID)
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+ return 1;
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+ if ((bcma_cc_read32(nflash->bcc, NAND_SPARE_RD0) & 0xff) != 0xff)
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+ return 1;
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+ }
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+ return 0;
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+}
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+
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+const char *part_probes[] = { "cmdlinepart", NULL };
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+static int bcm47xx_nflash_probe(struct platform_device *pdev)
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+{
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+ struct nand_chip *nchip;
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+ struct mtd_info *mtd;
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+ struct bcm47xx_nflash *nflash = dev_get_platdata(&pdev->dev);
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+ int ret = 0;
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+
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+ mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
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+ if (!mtd){
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+ ret = -ENOMEM;
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+ goto err_out;
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+ }
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+
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+ nchip = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
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+ if (!nchip) {
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+ ret = -ENOMEM;
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+ goto err_free_mtd;
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+ }
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+
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+ /* Register with MTD */
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+ mtd->priv = nchip;
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+ mtd->owner = THIS_MODULE;
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+ mtd->dev.parent = &pdev->dev;
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+
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+ /* 50 us command delay time */
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+ nchip->chip_delay = 50;
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+
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+ nchip->priv = nflash;
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+ nchip->dev_ready = bcm47xx_nflash_dev_ready;
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+ nchip->cmdfunc = bcm47xx_nflash_command;
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+ nchip->select_chip = bcm47xx_nflash_select_chip;
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+ nchip->read_byte = bcm47xx_nflash_read_byte;
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+ nchip->read_word = bcm47xx_nflash_read_word;
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+ nchip->write_buf = bcm47xx_nflash_write_buf;
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+ nchip->read_buf = bcm47xx_nflash_read_buf;
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+ nchip->verify_buf = bcm47xx_nflash_verify_buf;
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+ nchip->block_bad = bcm47xx_nflash_block_bad;
|
|
+ nchip->options = NAND_SKIP_BBTSCAN;
|
|
+
|
|
+ /* Not known */
|
|
+ nchip->ecc.mode = NAND_ECC_NONE;
|
|
+
|
|
+ /* first scan to find the device and get the page size */
|
|
+ if (nand_scan_ident(mtd, 1, NULL)) {
|
|
+ pr_err("nand_scan_ident failed\n");
|
|
+ ret = -ENXIO;
|
|
+ goto err_free_nchip;
|
|
+ }
|
|
+ nflash->size = mtd->size;
|
|
+ nflash->pagesize = 1 << nchip->page_shift;
|
|
+ nflash->blocksize = mtd->erasesize;
|
|
+ nflash->mtd = mtd;
|
|
+
|
|
+ /* second phase scan */
|
|
+ if (nand_scan_tail(mtd)) {
|
|
+ pr_err("nand_scan_tail failed\n");
|
|
+ ret = -ENXIO;
|
|
+ goto err_free_nchip;
|
|
+ }
|
|
+
|
|
+ mtd->name = "bcm47xx-nflash";
|
|
+ mtd->flags |= MTD_WRITEABLE;
|
|
+ ret = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
|
|
+
|
|
+ if (ret) {
|
|
+ pr_err("mtd_device_register failed\n");
|
|
+ goto err_free_nchip;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+
|
|
+err_free_nchip:
|
|
+ kfree(nchip);
|
|
+err_free_mtd:
|
|
+ kfree(mtd);
|
|
+err_out:
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static int __devexit bcm47xx_nflash_remove(struct platform_device *pdev)
|
|
+{
|
|
+ struct bcm47xx_nflash *nflash = dev_get_platdata(&pdev->dev);
|
|
+ struct mtd_info *mtd = nflash->mtd;
|
|
+
|
|
+ if (nflash) {
|
|
+ /* Release resources, unregister device */
|
|
+ nand_release(mtd);
|
|
+ kfree(mtd->priv);
|
|
+ kfree(mtd);
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct platform_device_id bcm47xx_nflash_table[] = {
|
|
+ { "bcm47xx-nflash", 0 },
|
|
+ { }
|
|
+};
|
|
+MODULE_DEVICE_TABLE(platform, bcm47xx_nflash_table);
|
|
+
|
|
+static struct platform_driver bcm47xx_nflash_driver = {
|
|
+ .id_table = bcm47xx_nflash_table,
|
|
+ .probe = bcm47xx_nflash_probe,
|
|
+ .remove = __devexit_p(bcm47xx_nflash_remove),
|
|
+ .driver = {
|
|
+ .name = "bcm47xx-nflash",
|
|
+ .owner = THIS_MODULE,
|
|
+ },
|
|
+};
|
|
+
|
|
+static int __init init_bcm47xx_nflash(void)
|
|
+{
|
|
+ int ret = platform_driver_register(&bcm47xx_nflash_driver);
|
|
+
|
|
+ if (ret)
|
|
+ pr_err("error registering platform driver: %i\n", ret);
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static void __exit exit_bcm47xx_nflash(void)
|
|
+{
|
|
+ platform_driver_unregister(&bcm47xx_nflash_driver);
|
|
+}
|
|
+
|
|
+module_init(init_bcm47xx_nflash);
|
|
+module_exit(exit_bcm47xx_nflash);
|
|
+
|
|
+MODULE_LICENSE("GPL");
|
|
+MODULE_DESCRIPTION("BCM47XX NAND flash driver");
|
|
--- /dev/null
|
|
+++ b/include/linux/mtd/bcm47xx_nand.h
|
|
@@ -0,0 +1,152 @@
|
|
+/*
|
|
+ * Broadcom chipcommon NAND flash interface
|
|
+ *
|
|
+ * Copyright (C) 2011-2012 Tathagata Das <tathagata@alumnux.com>
|
|
+ * Copyright (C) 2009, Broadcom Corporation
|
|
+ * All Rights Reserved.
|
|
+ *
|
|
+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
|
|
+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
|
|
+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
|
|
+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
|
|
+ *
|
|
+ */
|
|
+
|
|
+#ifndef LINUX_MTD_BCM47XX_NAND_H_
|
|
+#define LINUX_MTD_BCM47XX_NAND_H_
|
|
+
|
|
+#include <linux/mtd/mtd.h>
|
|
+
|
|
+#define NAND_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
|
|
+
|
|
+/* nand_cmd_start commands */
|
|
+#define NCMD_NULL 0
|
|
+#define NCMD_PAGE_RD 1
|
|
+#define NCMD_SPARE_RD 2
|
|
+#define NCMD_STATUS_RD 3
|
|
+#define NCMD_PAGE_PROG 4
|
|
+#define NCMD_SPARE_PROG 5
|
|
+#define NCMD_COPY_BACK 6
|
|
+#define NCMD_ID_RD 7
|
|
+#define NCMD_BLOCK_ERASE 8
|
|
+#define NCMD_FLASH_RESET 9
|
|
+#define NCMD_LOCK 0xa
|
|
+#define NCMD_LOCK_DOWN 0xb
|
|
+#define NCMD_UNLOCK 0xc
|
|
+#define NCMD_LOCK_STATUS 0xd
|
|
+
|
|
+/* nand_acc_control */
|
|
+#define NAC_RD_ECC_EN 0x80000000
|
|
+#define NAC_WR_ECC_EN 0x40000000
|
|
+#define NAC_RD_ECC_BLK0_EN 0x20000000
|
|
+#define NAC_FAST_PGM_RDIN 0x10000000
|
|
+#define NAC_RD_ERASED_ECC_EN 0x08000000
|
|
+#define NAC_PARTIAL_PAGE_EN 0x04000000
|
|
+#define NAC_PAGE_HIT_EN 0x01000000
|
|
+#define NAC_ECC_LEVEL0 0x00f00000
|
|
+#define NAC_ECC_LEVEL 0x000f0000
|
|
+#define NAC_SPARE_SIZE0 0x00003f00
|
|
+#define NAC_SPARE_SIZE 0x0000003f
|
|
+
|
|
+/* nand_config */
|
|
+#define NCF_CONFIG_LOCK 0x80000000
|
|
+#define NCF_BLOCK_SIZE_MASK 0x70000000
|
|
+#define NCF_BLOCK_SIZE_SHIFT 28
|
|
+#define NCF_DEVICE_SIZE_MASK 0x0f000000
|
|
+#define NCF_DEVICE_SIZE_SHIFT 24
|
|
+#define NCF_DEVICE_WIDTH 0x00800000
|
|
+#define NCF_PAGE_SIZE_MASK 0x00300000
|
|
+#define NCF_PAGE_SIZE_SHIFT 20
|
|
+#define NCF_FULL_ADDR_BYTES_MASK 0x00070000
|
|
+#define NCF_FULL_ADDR_BYTES_SHIFT 16
|
|
+#define NCF_COL_ADDR_BYTES_MASK 0x00007000
|
|
+#define NCF_COL_ADDR_BYTES_SHIFT 12
|
|
+#define NCF_BLK_ADDR_BYTES_MASK 0x00000700
|
|
+#define NCF_BLK_ADDR_BYTES_SHIFT 8
|
|
+
|
|
+/* nand_intfc_status */
|
|
+#define NIST_CTRL_READY 0x80000000
|
|
+#define NIST_FLASH_READY 0x40000000
|
|
+#define NIST_CACHE_VALID 0x20000000
|
|
+#define NIST_SPARE_VALID 0x10000000
|
|
+#define NIST_ERASED 0x08000000
|
|
+#define NIST_STATUS 0x000000ff
|
|
+
|
|
+#define NFL_SECTOR_SIZE 512
|
|
+
|
|
+#define NFL_TABLE_END 0xffffffff
|
|
+#define NFL_BOOT_SIZE 0x200000
|
|
+#define NFL_BOOT_OS_SIZE 0x2000000
|
|
+
|
|
+/* Nand flash MLC controller registers (corerev >= 38) */
|
|
+#define NAND_REVISION 0xC00
|
|
+#define NAND_CMD_START 0xC04
|
|
+#define NAND_CMD_ADDR_X 0xC08
|
|
+#define NAND_CMD_ADDR 0xC0C
|
|
+#define NAND_CMD_END_ADDR 0xC10
|
|
+#define NAND_CS_NAND_SELECT 0xC14
|
|
+#define NAND_CS_NAND_XOR 0xC18
|
|
+#define NAND_SPARE_RD0 0xC20
|
|
+#define NAND_SPARE_RD4 0xC24
|
|
+#define NAND_SPARE_RD8 0xC28
|
|
+#define NAND_SPARE_RD12 0xC2C
|
|
+#define NAND_SPARE_WR0 0xC30
|
|
+#define NAND_SPARE_WR4 0xC34
|
|
+#define NAND_SPARE_WR8 0xC38
|
|
+#define NAND_SPARE_WR12 0xC3C
|
|
+#define NAND_ACC_CONTROL 0xC40
|
|
+#define NAND_CONFIG 0xC48
|
|
+#define NAND_TIMING_1 0xC50
|
|
+#define NAND_TIMING_2 0xC54
|
|
+#define NAND_SEMAPHORE 0xC58
|
|
+#define NAND_DEVID 0xC60
|
|
+#define NAND_DEVID_X 0xC64
|
|
+#define NAND_BLOCK_LOCK_STATUS 0xC68
|
|
+#define NAND_INTFC_STATUS 0xC6C
|
|
+#define NAND_ECC_CORR_ADDR_X 0xC70
|
|
+#define NAND_ECC_CORR_ADDR 0xC74
|
|
+#define NAND_ECC_UNC_ADDR_X 0xC78
|
|
+#define NAND_ECC_UNC_ADDR 0xC7C
|
|
+#define NAND_READ_ERROR_COUNT 0xC80
|
|
+#define NAND_CORR_STAT_THRESHOLD 0xC84
|
|
+#define NAND_READ_ADDR_X 0xC90
|
|
+#define NAND_READ_ADDR 0xC94
|
|
+#define NAND_PAGE_PROGRAM_ADDR_X 0xC98
|
|
+#define NAND_PAGE_PROGRAM_ADDR 0xC9C
|
|
+#define NAND_COPY_BACK_ADDR_X 0xCA0
|
|
+#define NAND_COPY_BACK_ADDR 0xCA4
|
|
+#define NAND_BLOCK_ERASE_ADDR_X 0xCA8
|
|
+#define NAND_BLOCK_ERASE_ADDR 0xCAC
|
|
+#define NAND_INV_READ_ADDR_X 0xCB0
|
|
+#define NAND_INV_READ_ADDR 0xCB4
|
|
+#define NAND_BLK_WR_PROTECT 0xCC0
|
|
+#define NAND_ACC_CONTROL_CS1 0xCD0
|
|
+#define NAND_CONFIG_CS1 0xCD4
|
|
+#define NAND_TIMING_1_CS1 0xCD8
|
|
+#define NAND_TIMING_2_CS1 0xCDC
|
|
+#define NAND_SPARE_RD16 0xD30
|
|
+#define NAND_SPARE_RD20 0xD34
|
|
+#define NAND_SPARE_RD24 0xD38
|
|
+#define NAND_SPARE_RD28 0xD3C
|
|
+#define NAND_CACHE_ADDR 0xD40
|
|
+#define NAND_CACHE_DATA 0xD44
|
|
+#define NAND_CTRL_CONFIG 0xD48
|
|
+#define NAND_CTRL_STATUS 0xD4C
|
|
+
|
|
+struct bcma_drv_cc;
|
|
+
|
|
+struct bcm47xx_nflash {
|
|
+ struct bcma_drv_cc *bcc;
|
|
+
|
|
+ bool present;
|
|
+ bool boot; /* This is the flash the SoC boots from */
|
|
+ u32 blocksize; /* Block size */
|
|
+ u32 pagesize; /* Page size */
|
|
+
|
|
+ u32 size; /* Total size in bytes */
|
|
+ u32 next_opcode; /* Next expected command from upper NAND layer */
|
|
+
|
|
+ struct mtd_info *mtd;
|
|
+};
|
|
+
|
|
+#endif /* LINUX_MTD_BCM47XX_NAND_H_ */
|