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362 lines
9.2 KiB
Diff
362 lines
9.2 KiB
Diff
From a9ebdf9fa18fd317a4e97f46e8c5263898094864 Mon Sep 17 00:00:00 2001
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From: Yangbo Lu <yangbo.lu@nxp.com>
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Date: Mon, 25 Sep 2017 12:20:10 +0800
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Subject: [PATCH] cpufreq: support layerscape
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This is a integrated patch for layerscape pm support.
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Signed-off-by: Tang Yuantian <Yuantian.Tang@nxp.com>
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Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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---
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drivers/cpufreq/Kconfig | 2 +-
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drivers/cpufreq/qoriq-cpufreq.c | 176 +++++++++++++++-------------------------
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drivers/firmware/psci.c | 12 ++-
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3 files changed, 77 insertions(+), 113 deletions(-)
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--- a/drivers/cpufreq/Kconfig
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+++ b/drivers/cpufreq/Kconfig
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@@ -332,7 +332,7 @@ endif
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config QORIQ_CPUFREQ
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tristate "CPU frequency scaling driver for Freescale QorIQ SoCs"
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- depends on OF && COMMON_CLK && (PPC_E500MC || ARM)
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+ depends on OF && COMMON_CLK && (PPC_E500MC || ARM || ARM64)
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depends on !CPU_THERMAL || THERMAL
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select CLK_QORIQ
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help
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--- a/drivers/cpufreq/qoriq-cpufreq.c
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+++ b/drivers/cpufreq/qoriq-cpufreq.c
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@@ -11,6 +11,7 @@
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/clk.h>
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+#include <linux/clk-provider.h>
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#include <linux/cpufreq.h>
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#include <linux/cpu_cooling.h>
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#include <linux/errno.h>
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@@ -22,10 +23,6 @@
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#include <linux/slab.h>
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#include <linux/smp.h>
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-#if !defined(CONFIG_ARM)
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-#include <asm/smp.h> /* for get_hard_smp_processor_id() in UP configs */
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-#endif
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-
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/**
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* struct cpu_data
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* @pclk: the parent clock of cpu
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@@ -37,73 +34,51 @@ struct cpu_data {
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struct thermal_cooling_device *cdev;
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};
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+/*
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+ * Don't use cpufreq on this SoC -- used when the SoC would have otherwise
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+ * matched a more generic compatible.
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+ */
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+#define SOC_BLACKLIST 1
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+
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/**
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* struct soc_data - SoC specific data
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- * @freq_mask: mask the disallowed frequencies
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- * @flag: unique flags
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+ * @flags: SOC_xxx
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*/
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struct soc_data {
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- u32 freq_mask[4];
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- u32 flag;
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-};
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-
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-#define FREQ_MASK 1
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-/* see hardware specification for the allowed frqeuencies */
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-static const struct soc_data sdata[] = {
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- { /* used by p2041 and p3041 */
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- .freq_mask = {0x8, 0x8, 0x2, 0x2},
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- .flag = FREQ_MASK,
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- },
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- { /* used by p5020 */
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- .freq_mask = {0x8, 0x2},
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- .flag = FREQ_MASK,
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- },
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- { /* used by p4080, p5040 */
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- .freq_mask = {0},
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- .flag = 0,
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- },
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+ u32 flags;
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};
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-/*
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- * the minimum allowed core frequency, in Hz
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- * for chassis v1.0, >= platform frequency
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- * for chassis v2.0, >= platform frequency / 2
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- */
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-static u32 min_cpufreq;
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-static const u32 *fmask;
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-
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-#if defined(CONFIG_ARM)
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-static int get_cpu_physical_id(int cpu)
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-{
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- return topology_core_id(cpu);
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-}
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-#else
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-static int get_cpu_physical_id(int cpu)
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-{
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- return get_hard_smp_processor_id(cpu);
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-}
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-#endif
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-
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static u32 get_bus_freq(void)
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{
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struct device_node *soc;
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u32 sysfreq;
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+ struct clk *pltclk;
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+ int ret;
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+ /* get platform freq by searching bus-frequency property */
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soc = of_find_node_by_type(NULL, "soc");
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- if (!soc)
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- return 0;
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-
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- if (of_property_read_u32(soc, "bus-frequency", &sysfreq))
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- sysfreq = 0;
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+ if (soc) {
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+ ret = of_property_read_u32(soc, "bus-frequency", &sysfreq);
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+ of_node_put(soc);
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+ if (!ret)
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+ return sysfreq;
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+ }
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- of_node_put(soc);
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+ /* get platform freq by its clock name */
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+ pltclk = clk_get(NULL, "cg-pll0-div1");
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+ if (IS_ERR(pltclk)) {
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+ pr_err("%s: can't get bus frequency %ld\n",
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+ __func__, PTR_ERR(pltclk));
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+ return PTR_ERR(pltclk);
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+ }
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- return sysfreq;
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+ return clk_get_rate(pltclk);
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}
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-static struct device_node *cpu_to_clk_node(int cpu)
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+static struct clk *cpu_to_clk(int cpu)
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{
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- struct device_node *np, *clk_np;
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+ struct device_node *np;
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+ struct clk *clk;
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if (!cpu_present(cpu))
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return NULL;
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@@ -112,37 +87,28 @@ static struct device_node *cpu_to_clk_no
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if (!np)
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return NULL;
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- clk_np = of_parse_phandle(np, "clocks", 0);
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- if (!clk_np)
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- return NULL;
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-
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+ clk = of_clk_get(np, 0);
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of_node_put(np);
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-
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- return clk_np;
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+ return clk;
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}
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/* traverse cpu nodes to get cpu mask of sharing clock wire */
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static void set_affected_cpus(struct cpufreq_policy *policy)
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{
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- struct device_node *np, *clk_np;
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struct cpumask *dstp = policy->cpus;
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+ struct clk *clk;
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int i;
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- np = cpu_to_clk_node(policy->cpu);
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- if (!np)
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- return;
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-
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for_each_present_cpu(i) {
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- clk_np = cpu_to_clk_node(i);
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- if (!clk_np)
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+ clk = cpu_to_clk(i);
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+ if (IS_ERR(clk)) {
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+ pr_err("%s: no clock for cpu %d\n", __func__, i);
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continue;
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+ }
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- if (clk_np == np)
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+ if (clk_is_match(policy->clk, clk))
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cpumask_set_cpu(i, dstp);
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-
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- of_node_put(clk_np);
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}
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- of_node_put(np);
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}
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/* reduce the duplicated frequencies in frequency table */
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@@ -198,10 +164,11 @@ static void freq_table_sort(struct cpufr
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static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
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{
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- struct device_node *np, *pnode;
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+ struct device_node *np;
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int i, count, ret;
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- u32 freq, mask;
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+ u32 freq;
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struct clk *clk;
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+ const struct clk_hw *hwclk;
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struct cpufreq_frequency_table *table;
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struct cpu_data *data;
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unsigned int cpu = policy->cpu;
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@@ -221,17 +188,13 @@ static int qoriq_cpufreq_cpu_init(struct
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goto err_nomem2;
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}
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- pnode = of_parse_phandle(np, "clocks", 0);
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- if (!pnode) {
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- pr_err("%s: could not get clock information\n", __func__);
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- goto err_nomem2;
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- }
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+ hwclk = __clk_get_hw(policy->clk);
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+ count = clk_hw_get_num_parents(hwclk);
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- count = of_property_count_strings(pnode, "clock-names");
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data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
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if (!data->pclk) {
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pr_err("%s: no memory\n", __func__);
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- goto err_node;
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+ goto err_nomem2;
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}
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table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
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@@ -240,23 +203,11 @@ static int qoriq_cpufreq_cpu_init(struct
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goto err_pclk;
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}
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- if (fmask)
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- mask = fmask[get_cpu_physical_id(cpu)];
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- else
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- mask = 0x0;
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-
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for (i = 0; i < count; i++) {
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- clk = of_clk_get(pnode, i);
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+ clk = clk_hw_get_parent_by_index(hwclk, i)->clk;
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data->pclk[i] = clk;
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freq = clk_get_rate(clk);
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- /*
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- * the clock is valid if its frequency is not masked
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- * and large than minimum allowed frequency.
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- */
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- if (freq < min_cpufreq || (mask & (1 << i)))
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- table[i].frequency = CPUFREQ_ENTRY_INVALID;
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- else
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- table[i].frequency = freq / 1000;
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+ table[i].frequency = freq / 1000;
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table[i].driver_data = i;
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}
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freq_table_redup(table, count);
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@@ -282,7 +233,6 @@ static int qoriq_cpufreq_cpu_init(struct
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policy->cpuinfo.transition_latency = u64temp + 1;
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of_node_put(np);
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- of_node_put(pnode);
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return 0;
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@@ -290,10 +240,7 @@ err_nomem1:
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kfree(table);
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err_pclk:
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kfree(data->pclk);
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-err_node:
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- of_node_put(pnode);
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err_nomem2:
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- policy->driver_data = NULL;
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kfree(data);
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err_np:
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of_node_put(np);
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@@ -357,12 +304,25 @@ static struct cpufreq_driver qoriq_cpufr
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.attr = cpufreq_generic_attr,
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};
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+static const struct soc_data blacklist = {
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+ .flags = SOC_BLACKLIST,
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+};
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+
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static const struct of_device_id node_matches[] __initconst = {
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- { .compatible = "fsl,p2041-clockgen", .data = &sdata[0], },
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- { .compatible = "fsl,p3041-clockgen", .data = &sdata[0], },
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- { .compatible = "fsl,p5020-clockgen", .data = &sdata[1], },
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- { .compatible = "fsl,p4080-clockgen", .data = &sdata[2], },
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- { .compatible = "fsl,p5040-clockgen", .data = &sdata[2], },
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+ /* e6500 cannot use cpufreq due to erratum A-008083 */
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+ { .compatible = "fsl,b4420-clockgen", &blacklist },
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+ { .compatible = "fsl,b4860-clockgen", &blacklist },
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+ { .compatible = "fsl,t2080-clockgen", &blacklist },
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+ { .compatible = "fsl,t4240-clockgen", &blacklist },
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+
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+ { .compatible = "fsl,ls1012a-clockgen", },
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+ { .compatible = "fsl,ls1021a-clockgen", },
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+ { .compatible = "fsl,ls1043a-clockgen", },
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+ { .compatible = "fsl,ls1046a-clockgen", },
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+ { .compatible = "fsl,ls1088a-clockgen", },
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+ { .compatible = "fsl,ls2080a-clockgen", },
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+ { .compatible = "fsl,p4080-clockgen", },
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+ { .compatible = "fsl,qoriq-clockgen-1.0", },
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{ .compatible = "fsl,qoriq-clockgen-2.0", },
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{}
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};
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@@ -380,16 +340,12 @@ static int __init qoriq_cpufreq_init(voi
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match = of_match_node(node_matches, np);
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data = match->data;
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- if (data) {
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- if (data->flag)
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- fmask = data->freq_mask;
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- min_cpufreq = get_bus_freq();
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- } else {
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- min_cpufreq = get_bus_freq() / 2;
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- }
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of_node_put(np);
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+ if (data && data->flags & SOC_BLACKLIST)
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+ return -ENODEV;
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+
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ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
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if (!ret)
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pr_info("Freescale QorIQ CPU frequency scaling driver\n");
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--- a/drivers/firmware/psci.c
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+++ b/drivers/firmware/psci.c
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@@ -418,8 +418,12 @@ CPUIDLE_METHOD_OF_DECLARE(psci, "psci",
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static int psci_system_suspend(unsigned long unused)
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{
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- return invoke_psci_fn(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND),
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- virt_to_phys(cpu_resume), 0, 0);
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+ u32 state;
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+
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+ state = ( 2 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) |
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+ (1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT);
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+
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+ return psci_cpu_suspend(state, virt_to_phys(cpu_resume));
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}
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static int psci_system_suspend_enter(suspend_state_t state)
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@@ -439,6 +443,8 @@ static void __init psci_init_system_susp
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if (!IS_ENABLED(CONFIG_SUSPEND))
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return;
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+ suspend_set_ops(&psci_suspend_ops);
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+
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ret = psci_features(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND));
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if (ret != PSCI_RET_NOT_SUPPORTED)
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@@ -516,6 +522,8 @@ static void __init psci_0_2_set_function
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arm_pm_restart = psci_sys_reset;
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pm_power_off = psci_sys_poweroff;
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+ psci_init_system_suspend();
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+ suspend_set_ops(&psci_suspend_ops);
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}
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/*
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