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211 lines
4.5 KiB
Diff
211 lines
4.5 KiB
Diff
From cab1f4720e82f2e17eaeed9a9ad9e4f07c742977 Mon Sep 17 00:00:00 2001
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From: Mathieu Olivari <mathieu@codeaurora.org>
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Date: Mon, 11 May 2015 12:29:18 -0700
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Subject: [PATCH 8/8] ARM: dts: qcom: add gmac nodes to ipq806x platforms
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Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 31 ++++++++++++
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arch/arm/boot/dts/qcom-ipq8064-db149.dts | 43 ++++++++++++++++
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 86 ++++++++++++++++++++++++++++++++
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3 files changed, 160 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -64,6 +64,16 @@
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bias-disable;
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};
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};
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+
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+ rgmii2_pins: rgmii2_pins {
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+ mux {
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+ pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
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+ "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
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+ function = "rgmii2";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ };
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};
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gsbi@16300000 {
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@@ -177,5 +187,26 @@
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reg = <4>;
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};
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};
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+
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+ gmac1: ethernet@37200000 {
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+ status = "ok";
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+ phy-mode = "rgmii";
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+ phy-handle = <&phy4>;
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+ qcom,id = <1>;
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+
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+ pinctrl-0 = <&rgmii2_pins>;
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+ pinctrl-names = "default";
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+ };
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+
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+ gmac2: ethernet@37400000 {
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+ status = "ok";
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+ phy-mode = "sgmii";
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+ qcom,id = <2>;
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
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@@ -72,6 +72,14 @@
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bias-disable;
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};
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};
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+
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+ rgmii0_pins: rgmii0_pins {
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+ mux {
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+ pins = "gpio2", "gpio66";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ };
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};
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gsbi2: gsbi@12480000 {
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@@ -222,5 +230,40 @@
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reg = <7>;
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};
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};
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+
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+ gmac0: ethernet@37000000 {
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+ status = "ok";
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+ phy-mode = "rgmii";
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+ qcom,id = <0>;
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+ phy-handle = <&phy4>;
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+
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+ pinctrl-0 = <&rgmii0_pins>;
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+ pinctrl-names = "default";
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+ };
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+
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+ gmac1: ethernet@37200000 {
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+ status = "ok";
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+ phy-mode = "sgmii";
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+ qcom,id = <1>;
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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+
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+ gmac2: ethernet@37400000 {
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+ status = "ok";
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+ phy-mode = "sgmii";
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+ qcom,id = <2>;
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+ phy-handle = <&phy6>;
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+ };
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+
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+ gmac3: ethernet@37600000 {
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+ status = "ok";
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+ phy-mode = "sgmii";
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+ qcom,id = <3>;
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+ phy-handle = <&phy7>;
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -540,5 +540,91 @@
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status = "disabled";
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};
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+
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+ nss_common: syscon@03000000 {
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+ compatible = "syscon";
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+ reg = <0x03000000 0x0000FFFF>;
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+ };
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+
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+ qsgmii_csr: syscon@1bb00000 {
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+ compatible = "syscon";
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+ reg = <0x1bb00000 0x000001FF>;
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+ };
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+
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+ gmac0: ethernet@37000000 {
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+ device_type = "network";
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+ compatible = "qcom,ipq806x-gmac";
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+ reg = <0x37000000 0x200000>;
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+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "macirq";
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+
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+ qcom,nss-common = <&nss_common>;
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+ qcom,qsgmii-csr = <&qsgmii_csr>;
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+
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+ clocks = <&gcc GMAC_CORE1_CLK>;
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+ clock-names = "stmmaceth";
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+
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+ resets = <&gcc GMAC_CORE1_RESET>;
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+ reset-names = "stmmaceth";
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+
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+ status = "disabled";
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+ };
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+
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+ gmac1: ethernet@37200000 {
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+ device_type = "network";
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+ compatible = "qcom,ipq806x-gmac";
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+ reg = <0x37200000 0x200000>;
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+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "macirq";
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+
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+ qcom,nss-common = <&nss_common>;
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+ qcom,qsgmii-csr = <&qsgmii_csr>;
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+
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+ clocks = <&gcc GMAC_CORE2_CLK>;
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+ clock-names = "stmmaceth";
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+
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+ resets = <&gcc GMAC_CORE2_RESET>;
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+ reset-names = "stmmaceth";
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+
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+ status = "disabled";
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+ };
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+
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+ gmac2: ethernet@37400000 {
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+ device_type = "network";
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+ compatible = "qcom,ipq806x-gmac";
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+ reg = <0x37400000 0x200000>;
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+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "macirq";
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+
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+ qcom,nss-common = <&nss_common>;
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+ qcom,qsgmii-csr = <&qsgmii_csr>;
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+
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+ clocks = <&gcc GMAC_CORE3_CLK>;
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+ clock-names = "stmmaceth";
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+
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+ resets = <&gcc GMAC_CORE3_RESET>;
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+ reset-names = "stmmaceth";
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+
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+ status = "disabled";
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+ };
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+
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+ gmac3: ethernet@37600000 {
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+ device_type = "network";
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+ compatible = "qcom,ipq806x-gmac";
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+ reg = <0x37600000 0x200000>;
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+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "macirq";
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+
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+ qcom,nss-common = <&nss_common>;
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+ qcom,qsgmii-csr = <&qsgmii_csr>;
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+
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+ clocks = <&gcc GMAC_CORE4_CLK>;
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+ clock-names = "stmmaceth";
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+
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+ resets = <&gcc GMAC_CORE4_RESET>;
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+ reset-names = "stmmaceth";
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+
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+ status = "disabled";
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+ };
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};
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};
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