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124 lines
3.6 KiB
Diff
124 lines
3.6 KiB
Diff
From d31800ff6ed81f44488b590fe372e7b6572d2896 Mon Sep 17 00:00:00 2001
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From: Kristian Evensen <kristian.evensen@gmail.com>
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Date: Sun, 17 Jun 2018 14:18:45 +0200
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Subject: [PATCH] arm: dts: Add missing mt7623 pcie nodes
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---
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arch/arm/boot/dts/mt7623.dtsi | 105 ++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 105 insertions(+)
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--- a/arch/arm/boot/dts/mt7623.dtsi
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+++ b/arch/arm/boot/dts/mt7623.dtsi
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@@ -671,6 +671,111 @@
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#reset-cells = <1>;
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};
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+ pcie: pcie@1a140000 {
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+ compatible = "mediatek,mt7623-pcie";
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+ device_type = "pci";
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+ reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
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+ <0 0x1a142000 0 0x1000>, /* Port0 registers */
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+ <0 0x1a143000 0 0x1000>, /* Port1 registers */
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+ <0 0x1a144000 0 0x1000>; /* Port2 registers */
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+ reg-names = "subsys", "port0", "port1", "port2";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0xf800 0 0 0>;
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+ interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
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+ <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
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+ <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
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+ <&hifsys CLK_HIFSYS_PCIE0>,
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+ <&hifsys CLK_HIFSYS_PCIE1>,
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+ <&hifsys CLK_HIFSYS_PCIE2>;
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+ clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
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+ resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
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+ <&hifsys MT2701_HIFSYS_PCIE1_RST>,
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+ <&hifsys MT2701_HIFSYS_PCIE2_RST>;
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+ reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
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+ phys = <&pcie0_port PHY_TYPE_PCIE>,
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+ <&pcie1_port PHY_TYPE_PCIE>,
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+ <&u3port1 PHY_TYPE_PCIE>;
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+ phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
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+ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
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+ bus-range = <0x00 0xff>;
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+ status = "disabled";
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+ ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
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+ 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
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+
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+ pcie@0,0 {
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+ reg = <0x0000 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0>;
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+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
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+ ranges;
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+ num-lanes = <1>;
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+ status = "disabled";
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+ };
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+ pcie@1,0 {
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+ reg = <0x0800 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0>;
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+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
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+ ranges;
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+ num-lanes = <1>;
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+ status = "disabled";
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+ };
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+
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+ pcie@2,0 {
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+ reg = <0x1000 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0>;
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+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
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+ ranges;
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+ num-lanes = <1>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ pcie0_phy: pcie-phy@1a149000 {
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+ compatible = "mediatek,generic-tphy-v1";
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+ reg = <0 0x1a149000 0 0x0700>;
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+ status = "disabled";
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+
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+ pcie0_port: pcie-phy@1a149900 {
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+ reg = <0 0x1a149900 0 0x0700>;
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+ clocks = <&clk26m>;
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+ clock-names = "ref";
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+ #phy-cells = <1>;
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+ status = "okay";
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+ };
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+ };
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+
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+ pcie1_phy: pcie-phy@1a14a000 {
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+ compatible = "mediatek,generic-tphy-v1";
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+ reg = <0 0x1a14a000 0 0x0700>;
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+ status = "disabled";
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+
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+ pcie1_port: pcie-phy@1a14a900 {
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+ reg = <0 0x1a14a900 0 0x0700>;
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+ clocks = <&clk26m>;
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+ clock-names = "ref";
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+ #phy-cells = <1>;
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+ status = "okay";
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+ };
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+ };
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+
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+
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usb1: usb@1a1c0000 {
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compatible = "mediatek,mt7623-xhci",
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"mediatek,mt8173-xhci";
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