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535 lines
14 KiB
C
535 lines
14 KiB
C
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/*
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* MTD driver for the SPI Flash Memory support.
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*
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* Copyright (c) 2005-2006 Atheros Communications Inc.
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* Copyright (C) 2006 FON Technology, SL.
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* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
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*
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* This code is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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/*===========================================================================
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** !!!! VERY IMPORTANT NOTICE !!!! FLASH DATA STORED IN LITTLE ENDIAN FORMAT
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**
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** This module contains the Serial Flash access routines for the Atheros SOC.
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** The Atheros SOC integrates a SPI flash controller that is used to access
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** serial flash parts. The SPI flash controller executes in "Little Endian"
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** mode. THEREFORE, all WRITES and READS from the MIPS CPU must be
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** BYTESWAPPED! The SPI Flash controller hardware by default performs READ
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** ONLY byteswapping when accessed via the SPI Flash Alias memory region
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** (Physical Address 0x0800_0000 - 0x0fff_ffff). The data stored in the
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** flash sectors is stored in "Little Endian" format.
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**
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** The spiflash_write() routine performs byteswapping on all write
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** operations.
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**===========================================================================*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/version.h>
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#include <linux/errno.h>
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#include <linux/slab.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_device.h>
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#include <linux/squashfs_fs.h>
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#include <linux/root_dev.h>
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#include <asm/delay.h>
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#include <asm/io.h>
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#include "spiflash.h"
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/* debugging */
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/* #define SPIFLASH_DEBUG */
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#ifndef __BIG_ENDIAN
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#error This driver currently only works with big endian CPU.
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#endif
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#define MAX_PARTS 32
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static char module_name[] = "spiflash";
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#define MIN(a,b) ((a) < (b) ? (a) : (b))
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#define FALSE 0
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#define TRUE 1
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#define ROOTFS_NAME "rootfs"
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static __u32 spiflash_regread32(int reg);
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static void spiflash_regwrite32(int reg, __u32 data);
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static __u32 spiflash_sendcmd (int op);
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int __init spiflash_init (void);
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void __exit spiflash_exit (void);
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static int spiflash_probe_chip (void);
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static int spiflash_erase (struct mtd_info *mtd,struct erase_info *instr);
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static int spiflash_read (struct mtd_info *mtd, loff_t from,size_t len,size_t *retlen,u_char *buf);
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static int spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u_char *buf);
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/* Flash configuration table */
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struct flashconfig {
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__u32 byte_cnt;
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__u32 sector_cnt;
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__u32 sector_size;
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__u32 cs_addrmask;
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} flashconfig_tbl[MAX_FLASH] =
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{
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{ 0, 0, 0, 0},
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{ STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE, 0x0},
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{ STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE, 0x0},
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{ STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE, 0x0},
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{ STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE, 0x0}
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};
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/* Mapping of generic opcodes to STM serial flash opcodes */
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struct opcodes {
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__u16 code;
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__s8 tx_cnt;
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__s8 rx_cnt;
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} stm_opcodes[] = {
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{STM_OP_WR_ENABLE, 1, 0},
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{STM_OP_WR_DISABLE, 1, 0},
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{STM_OP_RD_STATUS, 1, 1},
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{STM_OP_WR_STATUS, 1, 0},
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{STM_OP_RD_DATA, 4, 4},
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{STM_OP_FAST_RD_DATA, 1, 0},
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{STM_OP_PAGE_PGRM, 8, 0},
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{STM_OP_SECTOR_ERASE, 4, 0},
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{STM_OP_BULK_ERASE, 1, 0},
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{STM_OP_DEEP_PWRDOWN, 1, 0},
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{STM_OP_RD_SIG, 4, 1}
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};
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/* Driver private data structure */
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struct spiflash_data {
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struct mtd_info *mtd;
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struct mtd_partition *parsed_parts; /* parsed partitions */
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void *spiflash_readaddr; /* memory mapped data for read */
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void *spiflash_mmraddr; /* memory mapped register space */
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spinlock_t mutex;
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};
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static struct spiflash_data *spidata;
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extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
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/***************************************************************************************************/
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static __u32
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spiflash_regread32(int reg)
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{
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volatile __u32 *data = (__u32 *)(spidata->spiflash_mmraddr + reg);
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return (*data);
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}
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static void
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spiflash_regwrite32(int reg, __u32 data)
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{
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volatile __u32 *addr = (__u32 *)(spidata->spiflash_mmraddr + reg);
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*addr = data;
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return;
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}
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static __u32
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spiflash_sendcmd (int op)
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{
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__u32 reg;
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__u32 mask;
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struct opcodes *ptr_opcode;
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ptr_opcode = &stm_opcodes[op];
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do {
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reg = spiflash_regread32(SPI_FLASH_CTL);
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} while (reg & SPI_CTL_BUSY);
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spiflash_regwrite32(SPI_FLASH_OPCODE, ptr_opcode->code);
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reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt |
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(ptr_opcode->rx_cnt << 4) | SPI_CTL_START;
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spiflash_regwrite32(SPI_FLASH_CTL, reg);
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if (ptr_opcode->rx_cnt > 0) {
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do {
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reg = spiflash_regread32(SPI_FLASH_CTL);
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} while (reg & SPI_CTL_BUSY);
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reg = (__u32) spiflash_regread32(SPI_FLASH_DATA);
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switch (ptr_opcode->rx_cnt) {
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case 1:
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mask = 0x000000ff;
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break;
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case 2:
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mask = 0x0000ffff;
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break;
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case 3:
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mask = 0x00ffffff;
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break;
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default:
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mask = 0xffffffff;
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break;
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}
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reg &= mask;
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}
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else {
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reg = 0;
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}
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return reg;
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}
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/* Probe SPI flash device
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* Function returns 0 for failure.
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* and flashconfig_tbl array index for success.
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*/
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static int
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spiflash_probe_chip (void)
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{
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__u32 sig;
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int flash_size;
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/* Read the signature on the flash device */
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sig = spiflash_sendcmd(SPI_RD_SIG);
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switch (sig) {
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case STM_8MBIT_SIGNATURE:
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flash_size = FLASH_1MB;
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break;
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case STM_16MBIT_SIGNATURE:
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flash_size = FLASH_2MB;
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break;
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case STM_32MBIT_SIGNATURE:
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flash_size = FLASH_4MB;
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break;
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case STM_64MBIT_SIGNATURE:
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flash_size = FLASH_8MB;
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break;
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default:
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printk (KERN_WARNING "%s: Read of flash device signature failed!\n", module_name);
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return (0);
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}
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return (flash_size);
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}
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static int
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spiflash_erase (struct mtd_info *mtd,struct erase_info *instr)
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{
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struct opcodes *ptr_opcode;
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__u32 temp, reg;
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int finished = FALSE;
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#ifdef SPIFLASH_DEBUG
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printk (KERN_DEBUG "%s(addr = 0x%.8x, len = %d)\n",__FUNCTION__,instr->addr,instr->len);
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#endif
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/* sanity checks */
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if (instr->addr + instr->len > mtd->size) return (-EINVAL);
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ptr_opcode = &stm_opcodes[SPI_SECTOR_ERASE];
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temp = ((__u32)instr->addr << 8) | (__u32)(ptr_opcode->code);
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spin_lock(&spidata->mutex);
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spiflash_sendcmd(SPI_WRITE_ENABLE);
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do {
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schedule();
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reg = spiflash_regread32(SPI_FLASH_CTL);
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} while (reg & SPI_CTL_BUSY);
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spiflash_regwrite32(SPI_FLASH_OPCODE, temp);
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reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt | SPI_CTL_START;
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spiflash_regwrite32(SPI_FLASH_CTL, reg);
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do {
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schedule();
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reg = spiflash_sendcmd(SPI_RD_STATUS);
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if (!(reg & SPI_STATUS_WIP)) {
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finished = TRUE;
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}
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} while (!finished);
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spin_unlock(&spidata->mutex);
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instr->state = MTD_ERASE_DONE;
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if (instr->callback) instr->callback (instr);
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#ifdef SPIFLASH_DEBUG
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printk (KERN_DEBUG "%s return\n",__FUNCTION__);
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#endif
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return (0);
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}
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static int
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spiflash_read (struct mtd_info *mtd, loff_t from,size_t len,size_t *retlen,u_char *buf)
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{
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u_char *read_addr;
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#ifdef SPIFLASH_DEBUG
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printk (KERN_DEBUG "%s(from = 0x%.8x, len = %d)\n",__FUNCTION__,(__u32) from,(int)len);
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#endif
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/* sanity checks */
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if (!len) return (0);
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if (from + len > mtd->size) return (-EINVAL);
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/* we always read len bytes */
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*retlen = len;
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read_addr = (u_char *)(spidata->spiflash_readaddr + from);
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spin_lock(&spidata->mutex);
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memcpy(buf, read_addr, len);
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spin_unlock(&spidata->mutex);
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return (0);
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}
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static int
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spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u_char *buf)
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{
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int done = FALSE, page_offset, bytes_left, finished;
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__u32 xact_len, spi_data = 0, opcode, reg;
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#ifdef SPIFLASH_DEBUG
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printk (KERN_DEBUG "%s(to = 0x%.8x, len = %d)\n",__FUNCTION__,(__u32) to,len);
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#endif
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*retlen = 0;
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/* sanity checks */
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if (!len) return (0);
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if (to + len > mtd->size) return (-EINVAL);
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opcode = stm_opcodes[SPI_PAGE_PROGRAM].code;
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bytes_left = len;
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while (done == FALSE) {
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xact_len = MIN(bytes_left, sizeof(__u32));
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/* 32-bit writes cannot span across a page boundary
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* (256 bytes). This types of writes require two page
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* program operations to handle it correctly. The STM part
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* will write the overflow data to the beginning of the
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* current page as opposed to the subsequent page.
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*/
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page_offset = (to & (STM_PAGE_SIZE - 1)) + xact_len;
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if (page_offset > STM_PAGE_SIZE) {
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xact_len -= (page_offset - STM_PAGE_SIZE);
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}
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spin_lock(&spidata->mutex);
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spiflash_sendcmd(SPI_WRITE_ENABLE);
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do {
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schedule();
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reg = spiflash_regread32(SPI_FLASH_CTL);
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} while (reg & SPI_CTL_BUSY);
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switch (xact_len) {
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case 1:
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spi_data = (u32) ((u8) *buf);
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break;
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case 2:
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spi_data = (buf[1] << 8) | buf[0];
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break;
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case 3:
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spi_data = (buf[2] << 16) | (buf[1] << 8) | buf[0];
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break;
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case 4:
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spi_data = (buf[3] << 24) | (buf[2] << 16) |
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(buf[1] << 8) | buf[0];
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break;
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default:
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printk("spiflash_write: default case\n");
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break;
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}
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spiflash_regwrite32(SPI_FLASH_DATA, spi_data);
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opcode = (opcode & SPI_OPCODE_MASK) | ((__u32)to << 8);
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spiflash_regwrite32(SPI_FLASH_OPCODE, opcode);
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reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | (xact_len + 4) | SPI_CTL_START;
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spiflash_regwrite32(SPI_FLASH_CTL, reg);
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finished = FALSE;
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do {
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schedule();
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reg = spiflash_sendcmd(SPI_RD_STATUS);
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if (!(reg & SPI_STATUS_WIP)) {
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finished = TRUE;
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}
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} while (!finished);
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spin_unlock(&spidata->mutex);
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bytes_left -= xact_len;
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to += xact_len;
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buf += xact_len;
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*retlen += xact_len;
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if (bytes_left == 0) {
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done = TRUE;
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}
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}
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return (0);
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}
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#ifdef CONFIG_MTD_PARTITIONS
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static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL };
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#endif
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static int spiflash_probe(struct platform_device *pdev)
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{
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int result = -1;
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int index, num_parts;
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struct mtd_info *mtd;
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spidata->spiflash_mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE);
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if (!spidata->spiflash_mmraddr) {
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printk (KERN_WARNING "%s: Failed to map flash device\n", module_name);
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kfree(spidata);
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spidata = NULL;
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}
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mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
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if (!mtd) {
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kfree(spidata);
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return (-ENXIO);
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}
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printk ("MTD driver for SPI flash.\n");
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printk ("%s: Probing for Serial flash ...\n", module_name);
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if (!(index = spiflash_probe_chip())) {
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printk (KERN_WARNING "%s: Found no serial flash device\n", module_name);
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kfree(mtd);
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kfree(spidata);
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return (-ENXIO);
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}
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printk ("%s: Found SPI serial Flash.\n", module_name);
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spidata->spiflash_readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt);
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if (!spidata->spiflash_readaddr) {
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printk (KERN_WARNING "%s: Failed to map flash device\n", module_name);
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kfree(mtd);
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kfree(spidata);
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return (-ENXIO);
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}
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mtd->name = module_name;
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mtd->type = MTD_NORFLASH;
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mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
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mtd->size = flashconfig_tbl[index].byte_cnt;
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mtd->erasesize = flashconfig_tbl[index].sector_size;
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mtd->writesize = 1;
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mtd->numeraseregions = 0;
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mtd->eraseregions = NULL;
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mtd->erase = spiflash_erase;
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mtd->read = spiflash_read;
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mtd->write = spiflash_write;
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mtd->owner = THIS_MODULE;
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#ifdef SPIFLASH_DEBUG
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printk (KERN_DEBUG
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"mtd->name = %s\n"
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"mtd->size = 0x%.8x (%uM)\n"
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"mtd->erasesize = 0x%.8x (%uK)\n"
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"mtd->numeraseregions = %d\n",
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mtd->name,
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mtd->size, mtd->size / (1024*1024),
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mtd->erasesize, mtd->erasesize / 1024,
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mtd->numeraseregions);
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if (mtd->numeraseregions) {
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for (result = 0; result < mtd->numeraseregions; result++) {
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printk (KERN_DEBUG
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"\n\n"
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"mtd->eraseregions[%d].offset = 0x%.8x\n"
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"mtd->eraseregions[%d].erasesize = 0x%.8x (%uK)\n"
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"mtd->eraseregions[%d].numblocks = %d\n",
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result,mtd->eraseregions[result].offset,
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result,mtd->eraseregions[result].erasesize,mtd->eraseregions[result].erasesize / 1024,
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result,mtd->eraseregions[result].numblocks);
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}
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}
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#endif
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/* parse redboot partitions */
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num_parts = parse_mtd_partitions(mtd, part_probe_types, &spidata->parsed_parts, 0);
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#ifdef SPIFLASH_DEBUG
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printk (KERN_DEBUG "Found %d partitions\n", num_parts);
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#endif
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if (num_parts) {
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result = add_mtd_partitions(mtd, spidata->parsed_parts, num_parts);
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} else {
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#ifdef SPIFLASH_DEBUG
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printk (KERN_DEBUG "Did not find any partitions\n");
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#endif
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kfree(mtd);
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kfree(spidata);
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return (-ENXIO);
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}
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spidata->mtd = mtd;
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return (result);
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}
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static int spiflash_remove (struct platform_device *pdev)
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{
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del_mtd_partitions (spidata->mtd);
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kfree(spidata->mtd);
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return 0;
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}
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struct platform_driver spiflash_driver = {
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.driver.name = "spiflash",
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.probe = spiflash_probe,
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.remove = spiflash_remove,
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};
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int __init
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spiflash_init (void)
|
|
{
|
|
spidata = kmalloc(sizeof(struct spiflash_data), GFP_KERNEL);
|
|
if (!spidata)
|
|
return (-ENXIO);
|
|
|
|
spin_lock_init(&spidata->mutex);
|
|
platform_driver_register(&spiflash_driver);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void __exit
|
|
spiflash_exit (void)
|
|
{
|
|
kfree(spidata);
|
|
}
|
|
|
|
module_init (spiflash_init);
|
|
module_exit (spiflash_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Atheros Communications Inc");
|
|
MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");
|
|
|