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183 lines
4.9 KiB
Diff
183 lines
4.9 KiB
Diff
--- a/drivers/mtd/nand/nand_base.c
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+++ b/drivers/mtd/nand/nand_base.c
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@@ -4249,6 +4249,8 @@ static inline bool is_full_id_nand(struc
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static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
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struct nand_flash_dev *type, const u8 *id_data, int *busw)
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{
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+ int mode;
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+
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if (!strncmp(type->id, id_data, type->id_len)) {
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mtd->writesize = type->pagesize;
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mtd->erasesize = type->erasesize;
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@@ -4259,8 +4261,9 @@ static bool find_full_id_nand(struct mtd
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chip->options |= type->options;
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chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
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chip->ecc_step_ds = NAND_ECC_STEP(type);
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- chip->onfi_timing_mode_default =
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- type->onfi_timing_mode_default;
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+
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+ mode = type->onfi_timing_mode_default;
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+ chip->sdr_timings = onfi_async_timing_mode_to_sdr_timings(mode);
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*busw = type->options & NAND_BUSWIDTH_16;
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--- a/drivers/mtd/nand/sunxi_nand.c
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+++ b/drivers/mtd/nand/sunxi_nand.c
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@@ -1425,7 +1425,7 @@ static int sunxi_nand_chip_init_timings(
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mode = onfi_get_async_timing_mode(&chip->nand);
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if (mode == ONFI_TIMING_MODE_UNKNOWN) {
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- mode = chip->nand.onfi_timing_mode_default;
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+ timings = chip->nand.sdr_timings;
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} else {
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uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
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@@ -1439,9 +1439,10 @@ static int sunxi_nand_chip_init_timings(
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feature);
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if (ret)
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return ret;
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+
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+ timings = onfi_async_timing_mode_to_sdr_timings(mode);
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}
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- timings = onfi_async_timing_mode_to_sdr_timings(mode);
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if (IS_ERR(timings))
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return PTR_ERR(timings);
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--- a/include/linux/mtd/nand.h
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+++ b/include/linux/mtd/nand.h
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@@ -612,6 +612,55 @@ struct nand_buffers {
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uint8_t *databuf;
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};
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+/*
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+ * struct nand_sdr_timings - SDR NAND chip timings
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+ *
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+ * This struct defines the timing requirements of a SDR NAND chip.
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+ * These informations can be found in every NAND datasheets and the timings
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+ * meaning are described in the ONFI specifications:
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+ * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
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+ * Parameters)
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+ *
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+ * All these timings are expressed in picoseconds.
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+ */
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+
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+struct nand_sdr_timings {
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+ u32 tALH_min;
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+ u32 tADL_min;
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+ u32 tALS_min;
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+ u32 tAR_min;
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+ u32 tCEA_max;
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+ u32 tCEH_min;
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+ u32 tCH_min;
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+ u32 tCHZ_max;
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+ u32 tCLH_min;
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+ u32 tCLR_min;
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+ u32 tCLS_min;
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+ u32 tCOH_min;
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+ u32 tCS_min;
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+ u32 tDH_min;
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+ u32 tDS_min;
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+ u32 tFEAT_max;
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+ u32 tIR_min;
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+ u32 tITC_max;
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+ u32 tRC_min;
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+ u32 tREA_max;
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+ u32 tREH_min;
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+ u32 tRHOH_min;
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+ u32 tRHW_min;
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+ u32 tRHZ_max;
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+ u32 tRLOH_min;
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+ u32 tRP_min;
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+ u32 tRR_min;
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+ u64 tRST_max;
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+ u32 tWB_max;
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+ u32 tWC_min;
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+ u32 tWH_min;
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+ u32 tWHR_min;
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+ u32 tWP_min;
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+ u32 tWW_min;
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+};
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+
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/**
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* struct nand_chip - NAND Private Flash Chip Data
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* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
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@@ -676,11 +725,7 @@ struct nand_buffers {
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* @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
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* also from the datasheet. It is the recommended ECC step
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* size, if known; if unknown, set to zero.
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- * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
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- * either deduced from the datasheet if the NAND
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- * chip is not ONFI compliant or set to 0 if it is
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- * (an ONFI chip is always configured in mode 0
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- * after a NAND reset)
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+ * @sdr_timings [INTERN] Pointer to default timings for SDR NAND.
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* @numchips: [INTERN] number of physical chips
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* @chipsize: [INTERN] the size of one chip for multichip arrays
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* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
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@@ -769,7 +814,7 @@ struct nand_chip {
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uint8_t bits_per_cell;
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uint16_t ecc_strength_ds;
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uint16_t ecc_step_ds;
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- int onfi_timing_mode_default;
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+ const struct nand_sdr_timings *sdr_timings;
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int badblockpos;
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int badblockbits;
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@@ -1156,55 +1201,6 @@ struct ofnandpart_data {
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int ofnandpart_parse(struct mtd_info *master,
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const struct ofnandpart_data *data);
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-/*
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- * struct nand_sdr_timings - SDR NAND chip timings
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- *
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- * This struct defines the timing requirements of a SDR NAND chip.
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- * These informations can be found in every NAND datasheets and the timings
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- * meaning are described in the ONFI specifications:
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- * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
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- * Parameters)
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- *
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- * All these timings are expressed in picoseconds.
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- */
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-
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-struct nand_sdr_timings {
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- u32 tALH_min;
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- u32 tADL_min;
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- u32 tALS_min;
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- u32 tAR_min;
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- u32 tCEA_max;
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- u32 tCEH_min;
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- u32 tCH_min;
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- u32 tCHZ_max;
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- u32 tCLH_min;
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- u32 tCLR_min;
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- u32 tCLS_min;
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- u32 tCOH_min;
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- u32 tCS_min;
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- u32 tDH_min;
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- u32 tDS_min;
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- u32 tFEAT_max;
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- u32 tIR_min;
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- u32 tITC_max;
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- u32 tRC_min;
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- u32 tREA_max;
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- u32 tREH_min;
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- u32 tRHOH_min;
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- u32 tRHW_min;
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- u32 tRHZ_max;
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- u32 tRLOH_min;
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- u32 tRP_min;
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- u32 tRR_min;
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- u64 tRST_max;
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- u32 tWB_max;
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- u32 tWC_min;
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- u32 tWH_min;
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- u32 tWHR_min;
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- u32 tWP_min;
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- u32 tWW_min;
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-};
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-
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/* get timing characteristics from ONFI timing mode. */
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const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
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#endif /* __LINUX_MTD_NAND_H */
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