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201 lines
5.8 KiB
Diff
201 lines
5.8 KiB
Diff
From a4df453fbfa6199ad33435cee6ce2dfcc65321b0 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 3 Jul 2015 05:45:58 +0200
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Subject: [PATCH 73/76] clk
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---
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include/dt-bindings/clock/mt7623-clk.h | 158 +++++++++++++++-----------------
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1 file changed, 73 insertions(+), 85 deletions(-)
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diff --git a/include/dt-bindings/clock/mt7623-clk.h b/include/dt-bindings/clock/mt7623-clk.h
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index cb1e8a9..410ef31 100644
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--- a/include/dt-bindings/clock/mt7623-clk.h
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+++ b/include/dt-bindings/clock/mt7623-clk.h
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@@ -17,96 +17,76 @@
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/* TOPCKGEN */
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-#define CLK_TOP_AUDPLL_24 1
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-#define CLK_TOP_AUDPLL_D16 2
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-#define CLK_TOP_AUDPLL_D4 3
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-#define CLK_TOP_AUDPLL_D8 4
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-#define CLK_TOP_CLKPH_MCK 5
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-#define CLK_TOP_CPUM_TCK_IN 6
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-#define CLK_TOP_DSI0_LNTC_DSICLK 7
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-#define CLK_TOP_HDMITX_CLKDIG_CTS 8
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-#define CLK_TOP_LVDS_ETH 9
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-#define CLK_TOP_LVDSPLL_D2 10
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-#define CLK_TOP_LVDSPLL_D4 11
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-#define CLK_TOP_LVDSPLL_D8 12
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-#define CLK_TOP_MAINPLL_230P3M 13
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-#define CLK_TOP_MAINPLL_322P4M 14
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-#define CLK_TOP_MAINPLL_537P3M 15
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-#define CLK_TOP_MAINPLL_806M 16
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-#define CLK_TOP_MEMPLL_MCK_D4 17
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-#define CLK_TOP_MMPLL_D2 18
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-#define CLK_TOP_MSDCPLL_D2 19
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-#define CLK_TOP_SYSPLL1_D16 20
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-#define CLK_TOP_SYSPLL1_D2 21
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-#define CLK_TOP_SYSPLL1_D4 22
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-#define CLK_TOP_SYSPLL1_D8 23
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-#define CLK_TOP_SYSPLL2_D2 24
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-#define CLK_TOP_SYSPLL2_D4 25
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-#define CLK_TOP_SYSPLL2_D8 26
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-#define CLK_TOP_SYSPLL3_D2 27
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-#define CLK_TOP_SYSPLL3_D4 28
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-#define CLK_TOP_SYSPLL4_D2 29
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-#define CLK_TOP_SYSPLL4_D4 30
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-#define CLK_TOP_SYSPLL_D3 31
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-#define CLK_TOP_SYSPLL_D5 32
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-#define CLK_TOP_SYSPLL_D7 33
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-#define CLK_TOP_TVDPLL_d2 34
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-#define CLK_TOP_TVDPLL_D4 35
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-#define CLK_TOP_UNIVPLL_178P3M 36
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-#define CLK_TOP_UNIVPLL1_D10 37
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-#define CLK_TOP_UNIVPLL1_D2 38
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-#define CLK_TOP_UNIVPLL1_D4 39
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-#define CLK_TOP_UNIVPLL1_D6 40
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-#define CLK_TOP_UNIVPLL1_D8 41
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-#define CLK_TOP_UNIVPLL_249P6M 42
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-#define CLK_TOP_UNIVPLL2_D2 43
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-#define CLK_TOP_UNIVPLL2_D4 44
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-#define CLK_TOP_UNIVPLL2_D6 45
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-#define CLK_TOP_UNIVPLL2_D8 46
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-#define CLK_TOP_UNIVPLL_416M 47
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-#define CLK_TOP_UNIVPLL_48M 48
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-#define CLK_TOP_UNIVPLL_624M 49
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-#define CLK_TOP_UNIVPLL_D26 50
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-#define CLK_TOP_UNIVPLL_D5 51
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-#define CLK_TOP_APLL_SEL 52
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+#define CLK_TOP_MAINPLL_650M 1
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+#define CLK_TOP_MAINPLL_433P3M 2
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+#define CLK_TOP_MAINPLL_260M 3
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+#define CLK_TOP_MAINPLL_185P6M 4
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+#define CLK_TOP_UNIVPLL_624M 5
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+#define CLK_TOP_UNIVPLL_416M 6
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+#define CLK_TOP_UNIVPLL_249P6M 7
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+#define CLK_TOP_UNIVPLL_178P3M 8
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+#define CLK_TOP_UNIVPLL_48M 9
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+#define CLK_TOP_AUDPLL_D4 10
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+#define CLK_TOP_AUDPLL_D8 11
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+#define CLK_TOP_AUDPLL_D16 12
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+#define CLK_TOP_AUDPLL_24 13
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+#define CLK_TOP_MSDCPLL_D2 14
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+#define CLK_TOP_SYSPLL1_D2 15
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+#define CLK_TOP_SYSPLL1_D4 16
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+#define CLK_TOP_SYSPLL1_D8 17
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+#define CLK_TOP_SYSPLL1_D16 18
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+#define CLK_TOP_SYSPLL2_D2 19
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+#define CLK_TOP_SYSPLL2_D4 20
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+#define CLK_TOP_SYSPLL2_D8 21
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+#define CLK_TOP_SYSPLL3_D2 22
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+#define CLK_TOP_SYSPLL3_D4 23
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+#define CLK_TOP_SYSPLL4_D2 24
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+#define CLK_TOP_SYSPLL4_D4 25
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+#define CLK_TOP_SYSPLL_D3 26
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+#define CLK_TOP_SYSPLL_D5 27
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+#define CLK_TOP_SYSPLL_D7 28
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+#define CLK_TOP_UNIVPLL1_D2 29
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+#define CLK_TOP_UNIVPLL1_D4 30
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+#define CLK_TOP_UNIVPLL1_D6 31
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+#define CLK_TOP_UNIVPLL1_D8 32
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+#define CLK_TOP_UNIVPLL1_D10 33
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+#define CLK_TOP_UNIVPLL2_D2 34
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+#define CLK_TOP_UNIVPLL2_D4 35
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+#define CLK_TOP_UNIVPLL2_D6 36
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+#define CLK_TOP_UNIVPLL2_D8 37
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+#define CLK_TOP_UNIVPLL_D5 38
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+#define CLK_TOP_UNIVPLL_D26 39
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+#define CLK_TOP_AXI_SEL 40
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+#define CLK_TOP_MEM_SEL 41
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+#define CLK_TOP_DDR_SEL 42
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+#define CLK_TOP_MM_SEL 43
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+#define CLK_TOP_PWM_SEL 44
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+#define CLK_TOP_MFG_SEL 45
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+#define CLK_TOP_UART_SEL 46
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+#define CLK_TOP_SPI_SEL 47
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+#define CLK_TOP_USB20_SEL 48
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+#define CLK_TOP_MSDC30_0_SEL 49
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+#define CLK_TOP_MSDC30_1_SEL 50
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+#define CLK_TOP_MSDC30_2_SEL 51
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+#define CLK_TOP_AUDIO_SEL 52
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#define CLK_TOP_AUDIO_INTBUS_SEL 53
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-#define CLK_TOP_AUDIO_SEL 54
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-#define CLK_TOP_AXI_SEL 55
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-#define CLK_TOP_CAM_SEL 56
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-#define CLK_TOP_DDR_SEL 57
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-#define CLK_TOP_DPI0_SEL 58
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-#define CLK_TOP_DPI1_SEL 59
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-#define CLK_TOP_DPILVDS_SEL 60
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-#define CLK_TOP_ETH_SEL 61
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-#define CLK_TOP_MEM_SEL 62
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-#define CLK_TOP_MFG_SEL 63
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-#define CLK_TOP_MM_SEL 64
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-#define CLK_TOP_MSDC30_0_SEL 65
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-#define CLK_TOP_MSDC30_1_SEL 66
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-#define CLK_TOP_MSDC30_2_SEL 67
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-#define CLK_TOP_NFI2X_SEL 68
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-#define CLK_TOP_PMICSPI_SEL 69
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-#define CLK_TOP_PWM_SEL 70
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-#define CLK_TOP_RTC_SEL 71
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-#define CLK_TOP_SCP_SEL 72
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-#define CLK_TOP_SPI_SEL 73
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-#define CLK_TOP_TVE_SEL 74
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-#define CLK_TOP_UART_SEL 75
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-#define CLK_TOP_USB20_SEL 76
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-#define CLK_TOP_VDEC_SEL 77
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-#define CLK_TOP_NR_CLK 78
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+#define CLK_TOP_PMICSPI_SEL 54
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+#define CLK_TOP_SCP_SEL 55
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+#define CLK_TOP_APLL_SEL 56
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+#define CLK_TOP_RTC_SEL 57
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+#define CLK_TOP_NFI2X_SEL 58
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+#define CLK_TOP_ETH_SEL 59
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+#define CLK_TOP_NR_CLK 60
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/* APMIXED_SYS */
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#define CLK_APMIXED_ARMPLL 1
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#define CLK_APMIXED_MAINPLL 2
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-#define CLK_APMIXED_MSDCPLL 3
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-#define CLK_APMIXED_UNIVPLL 4
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-#define CLK_APMIXED_MMPLL 5
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-#define CLK_APMIXED_VENCPLL 6
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-#define CLK_APMIXED_TVDPLL 7
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-#define CLK_APMIXED_LVDSPLL 8
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-#define CLK_APMIXED_AUDPLL 9
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+#define CLK_APMIXED_UNIVPLL 3
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+#define CLK_APMIXED_MSDCPLL 4
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+#define CLK_APMIXED_AUDPLL 5
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+#define CLK_APMIXED_TRGPLL 6
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+#define CLK_APMIXED_ETHPLL 7
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/* INFRA_SYS */
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@@ -124,7 +104,8 @@
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#define CLK_INFRA_IRRX 19
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#define CLK_INFRA_PMICSPI 22
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#define CLK_INFRA_PMIC_WRAP 23
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-#define CLK_INFRA_NR_CLK 24
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+#define CLK_INFRA_CA7SEL 24
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+#define CLK_INFRA_NR_CLK 25
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/* PERI_SYS */
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@@ -169,5 +150,12 @@
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#define CLK_PERI_UART3_SEL 38
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#define CLK_PERI_NR_CLK 39
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+#define CLK_HIFSYS_USB0_PHY 1
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+#define CLK_HIFSYS_USB1_PHY 2
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+#define CLK_HIFSYS_PCIE0 3
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+#define CLK_HIFSYS_PCIE1 4
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+#define CLK_HIFSYS_PCIE2 5
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+#define CLK_HIFSYS_NR_CLK 6
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+
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#endif /* _DT_BINDINGS_CLK_MT7623_H */
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--
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1.7.10.4
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