You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
40 lines
1.5 KiB
Diff
40 lines
1.5 KiB
Diff
From 6d3a47c29186aa8d26ff05a6209c94291ace0696 Mon Sep 17 00:00:00 2001
|
|
From: Chen-Yu Tsai <wens@csie.org>
|
|
Date: Sat, 5 Dec 2015 21:16:42 +0800
|
|
Subject: [PATCH] clk: sunxi: Add DRAM gates support for sun4i-a10
|
|
|
|
The A10/A20 share the same set of DRAM clock gates, which controls
|
|
direct memory access for some peripherals.
|
|
|
|
On the A10, bit 15 controls the system's DRAM clock output (possibly
|
|
to the DRAM chips), which we need to keep on.
|
|
|
|
On the A20 this has been moved to the DRAM controller, becoming a no-op.
|
|
However it is still listed in the user manual, so add it anyway.
|
|
|
|
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
|
|
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
---
|
|
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
|
|
drivers/clk/sunxi/clk-simple-gates.c | 12 ++++++++++++
|
|
2 files changed, 13 insertions(+)
|
|
|
|
--- a/drivers/clk/sunxi/clk-simple-gates.c
|
|
+++ b/drivers/clk/sunxi/clk-simple-gates.c
|
|
@@ -160,3 +160,15 @@ CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner
|
|
sun4i_a10_ahb_init);
|
|
CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",
|
|
sun4i_a10_ahb_init);
|
|
+
|
|
+static const int sun4i_a10_dram_critical_clocks[] __initconst = {
|
|
+ 15, /* dram_output */
|
|
+};
|
|
+
|
|
+static void __init sun4i_a10_dram_init(struct device_node *node)
|
|
+{
|
|
+ sunxi_simple_gates_setup(node, sun4i_a10_dram_critical_clocks,
|
|
+ ARRAY_SIZE(sun4i_a10_dram_critical_clocks));
|
|
+}
|
|
+CLK_OF_DECLARE(sun4i_a10_dram, "allwinner,sun4i-a10-dram-gates-clk",
|
|
+ sun4i_a10_dram_init);
|