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230 lines
6.4 KiB
Diff
230 lines
6.4 KiB
Diff
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
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+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
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@@ -13,14 +13,6 @@
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#ifndef _MT7620_REGS_H_
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#define _MT7620_REGS_H_
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-enum mt762x_soc_type {
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- MT762X_SOC_UNKNOWN = 0,
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- MT762X_SOC_MT7620A,
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- MT762X_SOC_MT7620N,
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- MT762X_SOC_MT7628AN,
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-};
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-extern enum mt762x_soc_type mt762x_soc;
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-
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#define MT7620_SYSC_BASE 0x10000000
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#define SYSC_REG_CHIP_NAME0 0x00
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--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
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+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
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@@ -13,6 +13,20 @@
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#ifndef _RALINK_REGS_H_
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#define _RALINK_REGS_H_
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+enum ralink_soc_type {
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+ RALINK_UNKNOWN = 0,
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+ RT305X_SOC_RT3050,
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+ RT305X_SOC_RT3052,
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+ RT305X_SOC_RT3350,
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+ RT305X_SOC_RT3352,
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+ RT305X_SOC_RT5350,
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+ MT762X_SOC_MT7620A,
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+ MT762X_SOC_MT7620N,
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+ MT762X_SOC_MT7621AT,
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+ MT762X_SOC_MT7628AN,
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+};
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+extern enum ralink_soc_type ralink_soc;
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+
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extern __iomem void *rt_sysc_membase;
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extern __iomem void *rt_memc_membase;
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--- a/arch/mips/include/asm/mach-ralink/rt305x.h
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+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
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@@ -13,25 +13,16 @@
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#ifndef _RT305X_REGS_H_
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#define _RT305X_REGS_H_
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-enum rt305x_soc_type {
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- RT305X_SOC_UNKNOWN = 0,
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- RT305X_SOC_RT3050,
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- RT305X_SOC_RT3052,
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- RT305X_SOC_RT3350,
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- RT305X_SOC_RT3352,
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- RT305X_SOC_RT5350,
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-};
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-
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-extern enum rt305x_soc_type rt305x_soc;
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+extern enum ralink_soc_type ralink_soc;
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static inline int soc_is_rt3050(void)
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{
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- return rt305x_soc == RT305X_SOC_RT3050;
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+ return ralink_soc == RT305X_SOC_RT3050;
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}
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static inline int soc_is_rt3052(void)
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{
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- return rt305x_soc == RT305X_SOC_RT3052;
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+ return ralink_soc == RT305X_SOC_RT3052;
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}
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static inline int soc_is_rt305x(void)
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@@ -41,17 +32,17 @@ static inline int soc_is_rt305x(void)
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static inline int soc_is_rt3350(void)
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{
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- return rt305x_soc == RT305X_SOC_RT3350;
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+ return ralink_soc == RT305X_SOC_RT3350;
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}
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static inline int soc_is_rt3352(void)
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{
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- return rt305x_soc == RT305X_SOC_RT3352;
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+ return ralink_soc == RT305X_SOC_RT3352;
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}
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static inline int soc_is_rt5350(void)
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{
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- return rt305x_soc == RT305X_SOC_RT5350;
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+ return ralink_soc == RT305X_SOC_RT5350;
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}
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#define RT305X_SYSC_BASE 0x10000000
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--- a/arch/mips/ralink/mt7620.c
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+++ b/arch/mips/ralink/mt7620.c
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@@ -43,8 +43,6 @@
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#define CLKCFG_FFRAC_MASK 0x001f
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#define CLKCFG_FFRAC_USB_VAL 0x0003
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-enum mt762x_soc_type mt762x_soc;
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-
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/* does the board have sdram or ddram */
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static int dram_type;
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@@ -375,7 +373,7 @@ void __init ralink_clk_init(void)
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#define RINT(x) ((x) / 1000000)
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#define RFRAC(x) (((x) / 1000) % 1000)
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- if (mt762x_soc == MT762X_SOC_MT7628AN) {
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+ if (ralink_soc == MT762X_SOC_MT7628AN) {
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if (xtal_rate == MHZ(40))
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cpu_rate = MHZ(580);
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else
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@@ -418,7 +416,7 @@ void __init ralink_clk_init(void)
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ralink_clk_add("10000c00.uartlite", periph_rate);
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ralink_clk_add("10180000.wmac", xtal_rate);
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- if (IS_ENABLED(CONFIG_USB) && mt762x_soc != MT762X_SOC_MT7628AN) {
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+ if (IS_ENABLED(CONFIG_USB) && ralink_soc != MT762X_SOC_MT7628AN) {
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/*
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* When the CPU goes into sleep mode, the BUS clock will be too low for
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* USB to function properly
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@@ -506,11 +504,11 @@ void prom_soc_init(struct ralink_soc_inf
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if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
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if (bga) {
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- mt762x_soc = MT762X_SOC_MT7620A;
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+ ralink_soc = MT762X_SOC_MT7620A;
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name = "MT7620A";
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soc_info->compatible = "ralink,mt7620a-soc";
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} else {
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- mt762x_soc = MT762X_SOC_MT7620N;
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+ ralink_soc = MT762X_SOC_MT7620N;
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name = "MT7620N";
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soc_info->compatible = "ralink,mt7620n-soc";
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#ifdef CONFIG_PCI
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@@ -518,7 +516,7 @@ void prom_soc_init(struct ralink_soc_inf
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#endif
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}
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} else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
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- mt762x_soc = MT762X_SOC_MT7628AN;
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+ ralink_soc = MT762X_SOC_MT7628AN;
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name = "MT7628AN";
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soc_info->compatible = "ralink,mt7628an-soc";
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} else {
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@@ -535,7 +533,7 @@ void prom_soc_init(struct ralink_soc_inf
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dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
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soc_info->mem_base = MT7620_DRAM_BASE;
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- if (mt762x_soc == MT762X_SOC_MT7628AN)
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+ if (ralink_soc == MT762X_SOC_MT7628AN)
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mt7628_dram_init(soc_info);
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else
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mt7620_dram_init(soc_info);
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@@ -548,7 +546,7 @@ void prom_soc_init(struct ralink_soc_inf
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pr_info("Digital PMU set to %s control\n",
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(pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
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- if (mt762x_soc == MT762X_SOC_MT7628AN)
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+ if (ralink_soc == MT762X_SOC_MT7628AN)
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rt2880_pinmux_data = mt7628an_pinmux_data;
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else
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rt2880_pinmux_data = mt7620a_pinmux_data;
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--- a/arch/mips/ralink/rt305x.c
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+++ b/arch/mips/ralink/rt305x.c
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@@ -21,8 +21,6 @@
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#include "common.h"
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-enum rt305x_soc_type rt305x_soc;
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-
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static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
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static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
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static struct rt2880_pmx_func uartf_func[] = {
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@@ -234,24 +232,24 @@ void prom_soc_init(struct ralink_soc_inf
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icache_sets = (read_c0_config1() >> 22) & 7;
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if (icache_sets == 1) {
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- rt305x_soc = RT305X_SOC_RT3050;
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+ ralink_soc = RT305X_SOC_RT3050;
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name = "RT3050";
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soc_info->compatible = "ralink,rt3050-soc";
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} else {
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- rt305x_soc = RT305X_SOC_RT3052;
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+ ralink_soc = RT305X_SOC_RT3052;
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name = "RT3052";
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soc_info->compatible = "ralink,rt3052-soc";
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}
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} else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
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- rt305x_soc = RT305X_SOC_RT3350;
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+ ralink_soc = RT305X_SOC_RT3350;
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name = "RT3350";
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soc_info->compatible = "ralink,rt3350-soc";
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} else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
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- rt305x_soc = RT305X_SOC_RT3352;
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+ ralink_soc = RT305X_SOC_RT3352;
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name = "RT3352";
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soc_info->compatible = "ralink,rt3352-soc";
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} else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
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- rt305x_soc = RT305X_SOC_RT5350;
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+ ralink_soc = RT305X_SOC_RT5350;
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name = "RT5350";
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soc_info->compatible = "ralink,rt5350-soc";
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} else {
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--- a/arch/mips/ralink/prom.c
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+++ b/arch/mips/ralink/prom.c
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@@ -15,9 +15,13 @@
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#include <asm/bootinfo.h>
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#include <asm/addrspace.h>
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+#include <asm/mach-ralink/ralink_regs.h>
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+
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#include "common.h"
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struct ralink_soc_info soc_info;
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+enum ralink_soc_type ralink_soc;
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+EXPORT_SYMBOL_GPL(ralink_soc);
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const char *get_system_type(void)
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{
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--- a/arch/mips/ralink/mt7621.c
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+++ b/arch/mips/ralink/mt7621.c
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@@ -175,6 +175,7 @@ void prom_soc_init(struct ralink_soc_inf
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soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
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soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
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soc_info->mem_base = MT7621_DRAM_BASE;
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+ ralink_soc = MT762X_SOC_MT7621AT;
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rt2880_pinmux_data = mt7621_pinmux_data;
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