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--- a/arch/mips/pci/pci-mt7620.c
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+++ b/arch/mips/pci/pci-mt7620.c
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@@ -33,7 +33,6 @@
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#define RALINK_GPIOMODE 0x60
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#define PPLL_CFG1 0x9c
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-#define PDRV_SW_SET BIT(23)
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#define PPLL_DRV 0xa0
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#define PDRV_SW_SET (1<<31)
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