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215 lines
6.3 KiB
Diff
215 lines
6.3 KiB
Diff
mtd: spi-nor: add support for switching between 3-byte and 4-byte addressing on w25q256 flash
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On some devices the flash chip needs to be in 3-byte addressing mode during
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reboot, otherwise the boot loader will fail to start.
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This mode however does not allow regular reads/writes onto the upper 16M
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half. W25Q256 has separate read commands for reading from >16M, however
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it does not have any separate write commands.
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This patch changes the code to leave the chip in 3-byte mode most of the
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time and only switch during erase/write cycles that go to >16M
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addresses.
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -89,6 +89,10 @@ struct flash_info {
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#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
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#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
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#define USE_CLSR BIT(14) /* use CLSR command */
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+#define SPI_NOR_4B_READ_OP BIT(15) /*
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+ * Like SPI_NOR_4B_OPCODES, but for read
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+ * op code only.
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+ */
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};
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#define JEDEC_MFR(info) ((info)->id[0])
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@@ -240,6 +244,15 @@ static inline u8 spi_nor_convert_3to4_er
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ARRAY_SIZE(spi_nor_3to4_erase));
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}
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+static void spi_nor_set_4byte_read(struct spi_nor *nor,
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+ const struct flash_info *info)
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+{
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+ nor->addr_width = 3;
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+ nor->ext_addr = 0;
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+ nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
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+ nor->flags |= SNOR_F_4B_EXT_ADDR;
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+}
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+
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static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
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const struct flash_info *info)
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{
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@@ -467,6 +480,36 @@ static int spi_nor_erase_sector(struct s
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return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
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}
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+static int spi_nor_check_ext_addr(struct spi_nor *nor, u32 addr)
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+{
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+ bool ext_addr;
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+ int ret;
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+ u8 cmd;
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+
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+ if (!(nor->flags & SNOR_F_4B_EXT_ADDR))
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+ return 0;
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+
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+ ext_addr = !!(addr & 0xff000000);
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+ if (nor->ext_addr == ext_addr)
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+ return 0;
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+
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+ cmd = ext_addr ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
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+ write_enable(nor);
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+ ret = nor->write_reg(nor, cmd, NULL, 0);
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+ if (ret)
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+ return ret;
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+
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+ cmd = 0;
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+ ret = nor->write_reg(nor, SPINOR_OP_WREAR, &cmd, 1);
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+ if (ret)
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+ return ret;
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+
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+ nor->addr_width = 3 + ext_addr;
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+ nor->ext_addr = ext_addr;
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+ write_disable(nor);
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+ return 0;
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+}
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+
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/*
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* Erase an address range on the nor chip. The address range may extend
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* one or more erase sectors. Return an error is there is a problem erasing.
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@@ -492,6 +535,10 @@ static int spi_nor_erase(struct mtd_info
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if (ret)
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return ret;
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+ ret = spi_nor_check_ext_addr(nor, addr + len);
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+ if (ret)
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+ return ret;
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+
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/* whole-chip erase? */
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if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
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unsigned long timeout;
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@@ -542,6 +589,7 @@ static int spi_nor_erase(struct mtd_info
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write_disable(nor);
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erase_err:
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+ spi_nor_check_ext_addr(nor, 0);
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spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
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instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE;
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@@ -834,7 +882,9 @@ static int spi_nor_lock(struct mtd_info
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if (ret)
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return ret;
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+ spi_nor_check_ext_addr(nor, ofs + len);
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ret = nor->flash_lock(nor, ofs, len);
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+ spi_nor_check_ext_addr(nor, 0);
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spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
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return ret;
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@@ -849,7 +899,9 @@ static int spi_nor_unlock(struct mtd_inf
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if (ret)
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return ret;
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+ spi_nor_check_ext_addr(nor, ofs + len);
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ret = nor->flash_unlock(nor, ofs, len);
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+ spi_nor_check_ext_addr(nor, 0);
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spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
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return ret;
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@@ -1164,7 +1216,7 @@ static const struct flash_info spi_nor_i
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{ "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
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{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
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{ "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
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- { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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+ { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_READ_OP) },
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{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
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SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
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@@ -1220,6 +1272,9 @@ static int spi_nor_read(struct mtd_info
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if (ret)
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return ret;
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+ if (nor->flags & SNOR_F_4B_EXT_ADDR)
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+ nor->addr_width = 4;
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+
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while (len) {
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loff_t addr = from;
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@@ -1244,6 +1299,18 @@ static int spi_nor_read(struct mtd_info
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ret = 0;
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read_err:
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+ if (nor->flags & SNOR_F_4B_EXT_ADDR) {
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+ u8 val = 0;
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+
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+ if ((from + len) & 0xff000000) {
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+ write_enable(nor);
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+ nor->write_reg(nor, SPINOR_OP_WREAR, &val, 1);
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+ write_disable(nor);
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+ }
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+
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+ nor->addr_width = 3;
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+ }
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+
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spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
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return ret;
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}
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@@ -1345,6 +1412,10 @@ static int spi_nor_write(struct mtd_info
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if (ret)
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return ret;
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+ ret = spi_nor_check_ext_addr(nor, to + len);
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+ if (ret < 0)
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+ return ret;
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+
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for (i = 0; i < len; ) {
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ssize_t written;
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loff_t addr = to + i;
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@@ -1385,6 +1456,7 @@ static int spi_nor_write(struct mtd_info
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}
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write_err:
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+ spi_nor_check_ext_addr(nor, 0);
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spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
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return ret;
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}
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@@ -2801,8 +2873,10 @@ int spi_nor_scan(struct spi_nor *nor, co
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} else if (mtd->size > 0x1000000) {
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/* enable 4-byte addressing if the device exceeds 16MiB */
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nor->addr_width = 4;
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- if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
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- info->flags & SPI_NOR_4B_OPCODES)
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+ if (info->flags & SPI_NOR_4B_READ_OP)
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+ spi_nor_set_4byte_read(nor, info);
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+ else if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
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+ info->flags & SPI_NOR_4B_OPCODES)
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spi_nor_set_4byte_opcodes(nor, info);
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else
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set_4byte(nor, info, 1);
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--- a/include/linux/mtd/spi-nor.h
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+++ b/include/linux/mtd/spi-nor.h
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@@ -102,6 +102,7 @@
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/* Used for Macronix and Winbond flashes. */
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#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
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#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
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+#define SPINOR_OP_WREAR 0xc5 /* Write extended address register */
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/* Used for Spansion flashes only. */
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#define SPINOR_OP_BRWR 0x17 /* Bank register write */
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@@ -229,6 +230,7 @@ enum spi_nor_option_flags {
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SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
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SNOR_F_READY_XSR_RDY = BIT(4),
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SNOR_F_USE_CLSR = BIT(5),
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+ SNOR_F_4B_EXT_ADDR = BIT(6),
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};
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/**
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@@ -280,6 +282,7 @@ struct spi_nor {
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enum spi_nor_protocol reg_proto;
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bool sst_write_second;
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u32 flags;
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+ u8 ext_addr;
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u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
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int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
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