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128 lines
3.4 KiB
C
128 lines
3.4 KiB
C
/* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
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* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
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* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
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*/
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#ifndef _RALINK_GSW_MT7620_H__
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#define _RALINK_GSW_MT7620_H__
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#define GSW_REG_PHY_TIMEOUT (5 * HZ)
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#ifdef CONFIG_SOC_MT7621
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#define MT7620A_GSW_REG_PIAC 0x0004
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#else
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#define MT7620A_GSW_REG_PIAC 0x7004
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#endif
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#define GSW_NUM_VLANS 16
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#define GSW_NUM_VIDS 4096
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#define GSW_NUM_PORTS 7
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#define GSW_PORT6 6
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#define GSW_MDIO_ACCESS BIT(31)
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#define GSW_MDIO_READ BIT(19)
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#define GSW_MDIO_WRITE BIT(18)
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#define GSW_MDIO_START BIT(16)
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#define GSW_MDIO_ADDR_SHIFT 20
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#define GSW_MDIO_REG_SHIFT 25
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#define GSW_REG_MIB_CNT_EN 0x4000
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#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
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#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
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#define GSW_REG_SMACCR0 0x3fE4
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#define GSW_REG_SMACCR1 0x3fE8
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#define GSW_REG_CKGCR 0x3ff0
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#define GSW_REG_IMR 0x7008
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#define GSW_REG_ISR 0x700c
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#define GSW_REG_GPC1 0x7014
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#define GSW_REG_MAC_P0_MCR 0x100
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#define GSW_REG_MAC_P1_MCR 0x200
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// Global MAC control register
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#define GSW_REG_GMACCR 0x30E0
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#define SYSC_REG_CHIP_REV_ID 0x0c
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#define SYSC_REG_CFG1 0x14
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#define RST_CTRL_MCM BIT(2)
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#define SYSC_PAD_RGMII2_MDIO 0x58
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#define SYSC_GPIO_MODE 0x60
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#define PORT_IRQ_ST_CHG 0x7f
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#ifdef CONFIG_SOC_MT7621
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#define ESW_PHY_POLLING 0x0000
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#else
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#define ESW_PHY_POLLING 0x7000
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#endif
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#define PMCR_IPG BIT(18)
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#define PMCR_MAC_MODE BIT(16)
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#define PMCR_FORCE BIT(15)
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#define PMCR_TX_EN BIT(14)
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#define PMCR_RX_EN BIT(13)
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#define PMCR_BACKOFF BIT(9)
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#define PMCR_BACKPRES BIT(8)
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#define PMCR_RX_FC BIT(5)
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#define PMCR_TX_FC BIT(4)
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#define PMCR_SPEED(_x) (_x << 2)
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#define PMCR_DUPLEX BIT(1)
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#define PMCR_LINK BIT(0)
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#define PHY_AN_EN BIT(31)
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#define PHY_PRE_EN BIT(30)
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#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
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enum {
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/* Global attributes. */
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GSW_ATTR_ENABLE_VLAN,
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/* Port attributes. */
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GSW_ATTR_PORT_UNTAG,
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};
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enum {
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PORT4_EPHY = 0,
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PORT4_EXT,
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};
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struct mt7620_gsw {
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struct device *dev;
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void __iomem *base;
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int irq;
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int port4;
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unsigned long int autopoll;
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};
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void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg);
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u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg);
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int mtk_gsw_init(struct fe_priv *priv);
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int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
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int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
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void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
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int mt7620_has_carrier(struct fe_priv *priv);
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void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
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int speed, int duplex);
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void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val);
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u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg);
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u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
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u32 phy_register, u32 write_data);
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u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg);
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void mt7620_handle_carrier(struct fe_priv *priv);
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#endif
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