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117 lines
3.9 KiB
Diff
117 lines
3.9 KiB
Diff
--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -538,6 +538,7 @@ static const struct spi_device_id spi_no
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/* GigaDevice */
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{ "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
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{ "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
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+ { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) },
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/* Intel/Numonyx -- xxxs33b */
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{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
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@@ -560,14 +561,14 @@ static const struct spi_device_id spi_no
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{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
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/* Micron */
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- { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
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- { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
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- { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
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- { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
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- { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
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- { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
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- { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, USE_FSR) },
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- { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, USE_FSR) },
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+ { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
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+ { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ) },
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+ { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
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+ { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
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+ { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
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+ { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
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+ { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
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+ { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
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/* PMC */
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{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
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@@ -890,6 +891,45 @@ static int spansion_quad_enable(struct s
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return 0;
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}
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+static int micron_quad_enable(struct spi_nor *nor)
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+{
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+ int ret;
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+ u8 val;
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+
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+ ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
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+ if (ret < 0) {
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+ dev_err(nor->dev, "error %d reading EVCR\n", ret);
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+ return ret;
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+ }
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+
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+ write_enable(nor);
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+
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+ /* set EVCR, enable quad I/O */
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+ nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
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+ ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1, 0);
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+ if (ret < 0) {
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+ dev_err(nor->dev, "error while writing EVCR register\n");
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+ return ret;
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+ }
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+
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+ ret = spi_nor_wait_till_ready(nor);
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+ if (ret)
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+ return ret;
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+
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+ /* read EVCR and check it */
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+ ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
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+ if (ret < 0) {
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+ dev_err(nor->dev, "error %d reading EVCR\n", ret);
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+ return ret;
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+ }
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+ if (val & EVCR_QUAD_EN_MICRON) {
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+ dev_err(nor->dev, "Micron EVCR Quad bit not clear\n");
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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static int set_quad_mode(struct spi_nor *nor, struct flash_info *info)
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{
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int status;
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@@ -902,6 +942,13 @@ static int set_quad_mode(struct spi_nor
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return -EINVAL;
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}
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return status;
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+ case CFI_MFR_ST:
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+ status = micron_quad_enable(nor);
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+ if (status) {
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+ dev_err(nor->dev, "Micron quad-read not enabled\n");
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+ return -EINVAL;
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+ }
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+ return status;
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default:
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status = spansion_quad_enable(nor);
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if (status) {
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--- a/include/linux/mtd/spi-nor.h
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+++ b/include/linux/mtd/spi-nor.h
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@@ -56,6 +56,10 @@
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/* Used for Spansion flashes only. */
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#define SPINOR_OP_BRWR 0x17 /* Bank register write */
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+/* Used for Micron flashes only. */
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+#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
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+#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
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+
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/* Status Register bits. */
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#define SR_WIP 1 /* Write in progress */
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#define SR_WEL 2 /* Write enable latch */
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@@ -67,6 +71,9 @@
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#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
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+/* Enhanced Volatile Configuration Register bits */
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+#define EVCR_QUAD_EN_MICRON 0x80 /* Micron Quad I/O */
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+
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/* Flag Status Register bits */
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#define FSR_READY 0x80
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