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250 lines
6.1 KiB
Diff
250 lines
6.1 KiB
Diff
From 07d7d95706c1bf373bd6b30c42f95c7b8dc8b9ce Mon Sep 17 00:00:00 2001
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From: Kumar Gala <galak@codeaurora.org>
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Date: Thu, 3 Apr 2014 14:48:22 -0500
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Subject: [PATCH 094/182] ARM: dts: qcom: Add initial APQ8064 SoC and IFC6410
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board device trees
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Add basic APQ8064 SoC include device tree and support for basic booting on
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the IFC6410 board. Also, keep dtb build list and qcom_dt_match in sorted
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order.
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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---
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arch/arm/boot/dts/Makefile | 8 +-
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arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 16 +++
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arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi | 1 +
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arch/arm/boot/dts/qcom-apq8064.dtsi | 170 ++++++++++++++++++++++++++++
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arch/arm/mach-qcom/board.c | 3 +-
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5 files changed, 194 insertions(+), 4 deletions(-)
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create mode 100644 arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
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create mode 100644 arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
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create mode 100644 arch/arm/boot/dts/qcom-apq8064.dtsi
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -231,9 +231,11 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420
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dra7-evm.dtb
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dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
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dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
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-dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
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- qcom-msm8960-cdp.dtb \
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- qcom-apq8074-dragonboard.dtb
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+dtb-$(CONFIG_ARCH_QCOM) += \
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+ qcom-apq8064-ifc6410.dtb \
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+ qcom-apq8074-dragonboard.dtb \
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+ qcom-msm8660-surf.dtb \
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+ qcom-msm8960-cdp.dtb
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dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
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ste-hrefprev60-stuib.dtb \
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ste-hrefprev60-tvk.dtb \
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--- /dev/null
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+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
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@@ -0,0 +1,16 @@
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+#include "qcom-apq8064-v2.0.dtsi"
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+
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+/ {
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+ model = "Qualcomm APQ8064/IFC6410";
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+ compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
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+
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+ soc {
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+ gsbi@16600000 {
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+ status = "ok";
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+ qcom,mode = <GSBI_PROT_I2C_UART>;
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+ serial@16640000 {
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+ status = "ok";
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+ };
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
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@@ -0,0 +1 @@
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+#include "qcom-apq8064.dtsi"
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--- /dev/null
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+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
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@@ -0,0 +1,170 @@
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+/dts-v1/;
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+
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+#include "skeleton.dtsi"
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+#include <dt-bindings/clock/qcom,gcc-msm8960.h>
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+#include <dt-bindings/soc/qcom,gsbi.h>
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+
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+/ {
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+ model = "Qualcomm APQ8064";
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+ compatible = "qcom,apq8064";
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+ interrupt-parent = <&intc>;
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpu@0 {
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+ compatible = "qcom,krait";
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+ enable-method = "qcom,kpss-acc-v1";
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+ device_type = "cpu";
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+ reg = <0>;
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc0>;
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+ qcom,saw = <&saw0>;
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+ };
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+
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+ cpu@1 {
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+ compatible = "qcom,krait";
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+ enable-method = "qcom,kpss-acc-v1";
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+ device_type = "cpu";
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+ reg = <1>;
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc1>;
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+ qcom,saw = <&saw1>;
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+ };
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+
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+ cpu@2 {
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+ compatible = "qcom,krait";
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+ enable-method = "qcom,kpss-acc-v1";
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+ device_type = "cpu";
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+ reg = <2>;
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc2>;
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+ qcom,saw = <&saw2>;
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+ };
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+
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+ cpu@3 {
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+ compatible = "qcom,krait";
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+ enable-method = "qcom,kpss-acc-v1";
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+ device_type = "cpu";
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+ reg = <3>;
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc3>;
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+ qcom,saw = <&saw3>;
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+ };
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+
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+ L2: l2-cache {
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+ compatible = "cache";
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+ cache-level = <2>;
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+ };
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+ };
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+
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+ cpu-pmu {
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+ compatible = "qcom,krait-pmu";
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+ interrupts = <1 10 0x304>;
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+ };
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+
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+ soc: soc {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ compatible = "simple-bus";
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+
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+ intc: interrupt-controller@2000000 {
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+ compatible = "qcom,msm-qgic2";
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ reg = <0x02000000 0x1000>,
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+ <0x02002000 0x1000>;
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+ };
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+
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+ timer@200a000 {
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+ compatible = "qcom,kpss-timer", "qcom,msm-timer";
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+ interrupts = <1 1 0x301>,
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+ <1 2 0x301>,
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+ <1 3 0x301>;
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+ reg = <0x0200a000 0x100>;
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+ clock-frequency = <27000000>,
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+ <32768>;
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+ cpu-offset = <0x80000>;
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+ };
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+
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+ acc0: clock-controller@2088000 {
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+ compatible = "qcom,kpss-acc-v1";
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+ reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
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+ };
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+
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+ acc1: clock-controller@2098000 {
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+ compatible = "qcom,kpss-acc-v1";
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+ reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
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+ };
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+
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+ acc2: clock-controller@20a8000 {
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+ compatible = "qcom,kpss-acc-v1";
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+ reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
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+ };
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+
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+ acc3: clock-controller@20b8000 {
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+ compatible = "qcom,kpss-acc-v1";
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+ reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
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+ };
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+
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+ saw0: regulator@2089000 {
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+ compatible = "qcom,saw2";
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+ reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
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+ regulator;
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+ };
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+
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+ saw1: regulator@2099000 {
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+ compatible = "qcom,saw2";
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+ reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
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+ regulator;
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+ };
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+
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+ saw2: regulator@20a9000 {
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+ compatible = "qcom,saw2";
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+ reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
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+ regulator;
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+ };
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+
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+ saw3: regulator@20b9000 {
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+ compatible = "qcom,saw2";
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+ reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
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+ regulator;
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+ };
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+
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+ gsbi7: gsbi@16600000 {
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+ status = "disabled";
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+ compatible = "qcom,gsbi-v1.0.0";
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+ reg = <0x16600000 0x100>;
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+ clocks = <&gcc GSBI7_H_CLK>;
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+ clock-names = "iface";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+
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+ serial@16640000 {
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+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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+ reg = <0x16640000 0x1000>,
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+ <0x16600000 0x1000>;
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+ interrupts = <0 158 0x0>;
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+ clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+ };
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+ };
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+
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+ qcom,ssbi@500000 {
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+ compatible = "qcom,ssbi";
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+ reg = <0x00500000 0x1000>;
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+ qcom,controller-type = "pmic-arbiter";
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+ };
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+
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+ gcc: clock-controller@900000 {
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+ compatible = "qcom,gcc-apq8064";
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+ reg = <0x00900000 0x4000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+ };
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+};
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--- a/arch/arm/mach-qcom/board.c
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+++ b/arch/arm/mach-qcom/board.c
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@@ -15,9 +15,10 @@
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#include <asm/mach/arch.h>
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static const char * const qcom_dt_match[] __initconst = {
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+ "qcom,apq8064",
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+ "qcom,apq8074-dragonboard",
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"qcom,msm8660-surf",
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"qcom,msm8960-cdp",
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- "qcom,apq8074-dragonboard",
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NULL
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};
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