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65 lines
2.8 KiB
Diff
65 lines
2.8 KiB
Diff
From 6bc13b1a867a5fd769f2be713ce9c9d863534bff Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.org>
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Date: Tue, 28 Aug 2018 10:40:40 +0100
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Subject: [PATCH] staging/vc04_services: Derive g_cache_line_size
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The ARM coprocessor registers include dcache line size, but there is no
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function to expose this value. Rather than create a new one, use the
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read_cpuid_id function to derive the correct value, which is 32 for
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BCM2835 and 64 for BCM2836/7.
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Signed-off-by: Phil Elwell <phil@raspberrypi.org>
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---
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.../interface/vchiq_arm/vchiq_2835_arm.c | 24 +++++++++++++++----
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1 file changed, 19 insertions(+), 5 deletions(-)
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--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
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+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c
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@@ -42,6 +42,7 @@
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#include <linux/uaccess.h>
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#include <linux/mm.h>
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#include <linux/of.h>
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+#include <asm/cputype.h>
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#include <soc/bcm2835/raspberrypi-firmware.h>
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#define TOTAL_SLOTS (VCHIQ_SLOT_ZERO_SLOTS + 2 * 32)
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@@ -81,13 +82,15 @@ static void __iomem *g_regs;
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* VPU firmware, which determines the required alignment of the
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* offsets/sizes in pagelists.
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*
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- * Modern VPU firmware looks for a DT "cache-line-size" property in
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- * the VCHIQ node and will overwrite it with the actual L2 cache size,
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+ * Previous VPU firmware looked for a DT "cache-line-size" property in
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+ * the VCHIQ node and would overwrite it with the actual L2 cache size,
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* which the kernel must then respect. That property was rejected
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- * upstream, so we have to use the VPU firmware's compatibility value
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- * of 32.
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+ * upstream, so we now rely on both sides to "do the right thing" independently
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+ * of the other. To improve backwards compatibility, this new behaviour is
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+ * signalled to the firmware by the use of a corrected "reg" property on the
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+ * relevant Device Tree node.
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*/
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-static unsigned int g_cache_line_size = 32;
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+static unsigned int g_cache_line_size;
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static unsigned int g_fragments_size;
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static char *g_fragments_base;
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static char *g_free_fragments;
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@@ -127,6 +130,17 @@ int vchiq_platform_init(struct platform_
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if (err < 0)
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return err;
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+ /*
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+ * The tempting L1_CACHE_BYTES macro doesn't work in the case of
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+ * a kernel built with bcm2835_defconfig running on a BCM2836/7
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+ * processor, hence the need for a runtime check. The dcache line size
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+ * is encoded in one of the coprocessor registers, but there is no
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+ * convenient way to access it short of embedded assembler, hence
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+ * the use of read_cpuid_id(). The following test evaluates to true
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+ * on a BCM2835 showing that it is ARMv6-ish, whereas
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+ * cpu_architecture() will indicate that it is an ARMv7.
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+ */
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+ g_cache_line_size = ((read_cpuid_id() & 0x7f000) == 0x7b000) ? 32 : 64;
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g_fragments_size = 2 * g_cache_line_size;
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/* Allocate space for the channels in coherent memory */
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