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596 lines
13 KiB
C
596 lines
13 KiB
C
/*
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* ADMTEK Adm6996 switch configuration module
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*
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* Copyright (C) 2005 Felix Fietkau <nbd@nbd.name>
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*
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* Partially based on Broadcom Home Networking Division 10/100 Mbit/s
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* Ethernet Device Driver (from Montavista 2.4.20_mvl31 Kernel).
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* Copyright (C) 2004 Broadcom Corporation
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*
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* adm_rreg function from adm6996
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* Copyright (C) 2004 Nikki Chumakov <nikki@gattaca.ru>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/if.h>
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#include <linux/if_arp.h>
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#include <linux/sockios.h>
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#include <linux/delay.h>
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#include <asm/uaccess.h>
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#include "switch-core.h"
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#include "gpio.h"
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#ifdef CONFIG_BCM47XX
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#include <nvram.h>
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#endif
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#define DRIVER_NAME "adm6996"
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#define DRIVER_VERSION "0.01"
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static int eecs = 0;
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static int eesk = 0;
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static int eedi = 0;
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static int eerc = 0;
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static int force = 0;
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MODULE_AUTHOR("Felix Fietkau <openwrt@nbd.name>");
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MODULE_LICENSE("GPL");
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module_param(eecs, int, 0);
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module_param(eesk, int, 0);
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module_param(eedi, int, 0);
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module_param(eerc, int, 0);
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module_param(force, int, 0);
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/* Minimum timing constants */
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#define EECK_EDGE_TIME 3 /* 3us - max(adm 2.5us, 93c 1us) */
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#define EEDI_SETUP_TIME 1 /* 1us - max(adm 10ns, 93c 400ns) */
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#define EECS_SETUP_TIME 1 /* 1us - max(adm no, 93c 200ns) */
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/* Handy macros for writing fixed length values */
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#define adm_write8(cs, b) { __u8 val = (__u8) (b); adm_write(cs, &val, sizeof(val)*8); }
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#define adm_write16(cs, w) { __u16 val = hton16(w); adm_write(cs, (__u8 *)&val, sizeof(val)*8); }
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#define adm_write32(cs, i) { uint32 val = hton32(i); adm_write(cs, (__u8 *)&val, sizeof(val)*8); }
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#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
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#ifdef CONFIG_BCM47XX
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/* Return gpio pin number assigned to the named pin */
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/*
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* Variable should be in format:
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*
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* gpio<N>=pin_name
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*
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* 'def_pin' is returned if there is no such variable found.
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*/
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static unsigned int get_gpiopin(char *pin_name, unsigned int def_pin)
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{
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char name[] = "gpioXXXX";
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char val[10];
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unsigned int pin;
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/* Go thru all possibilities till a match in pin name */
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for (pin = 0; pin < 16; pin ++) {
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sprintf(name, "gpio%d", pin);
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if (nvram_getenv(name, val, sizeof(val)) >= 0) {
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if (!strcmp(val, pin_name))
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return pin;
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}
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}
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return def_pin;
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}
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#endif
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static void adm_write(int cs, char *buf, unsigned int bits)
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{
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int i, len = (bits + 7) / 8;
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__u8 mask;
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gpio_out(eecs, (cs ? eecs : 0));
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udelay(EECK_EDGE_TIME);
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/* Byte assemble from MSB to LSB */
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for (i = 0; i < len; i++) {
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/* Bit bang from MSB to LSB */
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for (mask = 0x80; mask && bits > 0; mask >>= 1, bits --) {
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/* Clock low */
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gpio_out(eesk, 0);
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udelay(EECK_EDGE_TIME);
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/* Output on rising edge */
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gpio_out(eedi, ((mask & buf[i]) ? eedi : 0));
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udelay(EEDI_SETUP_TIME);
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/* Clock high */
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gpio_out(eesk, eesk);
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udelay(EECK_EDGE_TIME);
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}
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}
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/* Clock low */
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gpio_out(eesk, 0);
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udelay(EECK_EDGE_TIME);
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if (cs)
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gpio_out(eecs, 0);
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}
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static void adm_read(int cs, char *buf, unsigned int bits)
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{
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int i, len = (bits + 7) / 8;
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__u8 mask;
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gpio_out(eecs, (cs ? eecs : 0));
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udelay(EECK_EDGE_TIME);
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/* Byte assemble from MSB to LSB */
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for (i = 0; i < len; i++) {
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__u8 byte;
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/* Bit bang from MSB to LSB */
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for (mask = 0x80, byte = 0; mask && bits > 0; mask >>= 1, bits --) {
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__u8 gp;
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/* Clock low */
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gpio_out(eesk, 0);
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udelay(EECK_EDGE_TIME);
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/* Input on rising edge */
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gp = gpio_in();
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if (gp & eedi)
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byte |= mask;
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/* Clock high */
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gpio_out(eesk, eesk);
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udelay(EECK_EDGE_TIME);
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}
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*buf++ = byte;
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}
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/* Clock low */
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gpio_out(eesk, 0);
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udelay(EECK_EDGE_TIME);
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if (cs)
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gpio_out(eecs, 0);
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}
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/* Enable outputs with specified value to the chip */
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static void adm_enout(__u8 pins, __u8 val)
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{
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/* Prepare GPIO output value */
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gpio_out(pins, val);
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/* Enable GPIO outputs */
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gpio_outen(pins, pins);
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udelay(EECK_EDGE_TIME);
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}
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/* Disable outputs to the chip */
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static void adm_disout(__u8 pins)
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{
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/* Disable GPIO outputs */
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gpio_outen(pins, 0);
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udelay(EECK_EDGE_TIME);
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}
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/* Advance clock(s) */
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static void adm_adclk(int clocks)
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{
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int i;
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for (i = 0; i < clocks; i++) {
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/* Clock high */
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gpio_out(eesk, eesk);
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udelay(EECK_EDGE_TIME);
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/* Clock low */
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gpio_out(eesk, 0);
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udelay(EECK_EDGE_TIME);
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}
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}
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static __u32 adm_rreg(__u8 table, __u8 addr)
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{
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/* cmd: 01 10 T DD R RRRRRR */
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__u8 bits[6] = {
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0xFF, 0xFF, 0xFF, 0xFF,
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(0x06 << 4) | ((table & 0x01) << 3 | (addr&64)>>6),
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((addr&63)<<2)
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};
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__u8 rbits[4];
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/* Enable GPIO outputs with all pins to 0 */
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adm_enout((__u8)(eecs | eesk | eedi), 0);
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adm_write(0, bits, 46);
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adm_disout((__u8)(eedi));
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adm_adclk(2);
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adm_read (0, rbits, 32);
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/* Extra clock(s) required per datasheet */
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adm_adclk(2);
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/* Disable GPIO outputs */
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adm_disout((__u8)(eecs | eesk));
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if (!table) /* EEPROM has 16-bit registers, but pumps out two registers in one request */
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return (addr & 0x01 ? (rbits[0]<<8) | rbits[1] : (rbits[2]<<8) | (rbits[3]));
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else
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return (rbits[0]<<24) | (rbits[1]<<16) | (rbits[2]<<8) | rbits[3];
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}
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/* Write chip configuration register */
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/* Follow 93c66 timing and chip's min EEPROM timing requirement */
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void
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adm_wreg(__u8 addr, __u16 val)
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{
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/* cmd(27bits): sb(1) + opc(01) + addr(bbbbbbbb) + data(bbbbbbbbbbbbbbbb) */
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__u8 bits[4] = {
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(0x05 << 5) | (addr >> 3),
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(addr << 5) | (__u8)(val >> 11),
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(__u8)(val >> 3),
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(__u8)(val << 5)
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};
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/* Enable GPIO outputs with all pins to 0 */
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adm_enout((__u8)(eecs | eesk | eedi), 0);
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/* Write cmd. Total 27 bits */
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adm_write(1, bits, 27);
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/* Extra clock(s) required per datasheet */
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adm_adclk(2);
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/* Disable GPIO outputs */
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adm_disout((__u8)(eecs | eesk | eedi));
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}
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/* Port configuration registers */
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static int port_conf[] = { 0x01, 0x03, 0x05, 0x07, 0x08, 0x09 };
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/* Bits in VLAN port mapping */
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static int vlan_ports[] = { 1 << 0, 1 << 2, 1 << 4, 1 << 6, 1 << 7, 1 << 8 };
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static int handle_vlan_port_read(void *driver, char *buf, int nr)
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{
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int ports, i, c, len = 0;
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if ((nr < 0) || (nr > 15))
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return 0;
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/* Get VLAN port map */
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ports = adm_rreg(0, 0x13 + nr);
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for (i = 0; i <= 5; i++) {
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if (ports & vlan_ports[i]) {
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c = adm_rreg(0, port_conf[i]);
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len += sprintf(buf + len, "%d", i);
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if (c & (1 << 4)) {
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buf[len++] = 't';
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if (((c & (0xf << 10)) >> 10) == nr)
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buf[len++] = '*';
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} else if (i == 5)
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buf[len++] = 'u';
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buf[len++] = '\t';
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}
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}
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len += sprintf(buf + len, "\n");
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return len;
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}
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static int handle_vlan_port_write(void *driver, char *buf, int nr)
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{
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int i, cfg, ports;
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switch_driver *d = (switch_driver *) driver;
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switch_vlan_config *c = switch_parse_vlan(d, buf);
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if (c == NULL)
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return -1;
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ports = adm_rreg(0, 0x13 + nr);
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for (i = 0; i < d->ports; i++) {
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if (c->port & (1 << i)) {
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ports |= vlan_ports[i];
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cfg = adm_rreg(0, port_conf[i]);
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/* Tagging */
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if (c->untag & (1 << i))
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cfg &= ~(1 << 4);
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else
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cfg |= (1 << 4);
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if ((c->untag | c->pvid) & (1 << i)) {
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cfg = (cfg & ~(0xf << 10)) | (nr << 10);
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}
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adm_wreg(port_conf[i], (__u16) cfg);
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} else {
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ports &= ~(vlan_ports[i]);
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}
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}
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adm_wreg(0x13 + nr, (__u16) ports);
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kfree(c);
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return 0;
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}
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static int handle_port_enable_read(void *driver, char *buf, int nr)
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{
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return sprintf(buf, "%d\n", ((adm_rreg(0, port_conf[nr]) & (1 << 5)) ? 0 : 1));
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}
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static int handle_port_enable_write(void *driver, char *buf, int nr)
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{
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int reg = adm_rreg(0, port_conf[nr]);
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if (buf[0] == '0')
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reg |= (1 << 5);
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else if (buf[0] == '1')
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reg &= ~(1 << 5);
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else return -1;
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adm_wreg(port_conf[nr], (__u16) reg);
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return 0;
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}
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static int handle_port_media_read(void *driver, char *buf, int nr)
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{
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int len;
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int media = 0;
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int reg = adm_rreg(0, port_conf[nr]);
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if (reg & (1 << 1))
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media |= SWITCH_MEDIA_AUTO;
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if (reg & (1 << 2))
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media |= SWITCH_MEDIA_100;
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if (reg & (1 << 3))
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media |= SWITCH_MEDIA_FD;
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len = switch_print_media(buf, media);
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return len + sprintf(buf + len, "\n");
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}
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static int handle_port_media_write(void *driver, char *buf, int nr)
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{
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int media = switch_parse_media(buf);
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int reg = adm_rreg(0, port_conf[nr]);
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if (media < 0)
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return -1;
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reg &= ~((1 << 1) | (1 << 2) | (1 << 3));
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if (media & SWITCH_MEDIA_AUTO)
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reg |= 1 << 1;
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if (media & SWITCH_MEDIA_100)
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reg |= 1 << 2;
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if (media & SWITCH_MEDIA_FD)
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reg |= 1 << 3;
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adm_wreg(port_conf[nr], reg);
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return 0;
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}
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static int handle_vlan_enable_read(void *driver, char *buf, int nr)
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{
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return sprintf(buf, "%d\n", ((adm_rreg(0, 0x11) & (1 << 5)) ? 1 : 0));
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}
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static int handle_vlan_enable_write(void *driver, char *buf, int nr)
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{
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int reg = adm_rreg(0, 0x11);
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if (buf[0] == '1')
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reg |= (1 << 5);
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else if (buf[0] == '0')
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reg &= ~(1 << 5);
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else return -1;
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adm_wreg(0x11, (__u16) reg);
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return 0;
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}
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static int handle_reset(void *driver, char *buf, int nr)
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{
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int i;
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u32 cfg;
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/*
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* Reset sequence: RC high->low(100ms)->high(30ms)
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*
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* WAR: Certain boards don't have the correct power on
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* reset logic therefore we must explicitly perform the
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* sequence in software.
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*/
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if (eerc) {
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/* Keep RC high for at least 20ms */
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adm_enout(eerc, eerc);
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for (i = 0; i < 20; i ++)
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udelay(1000);
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/* Keep RC low for at least 100ms */
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adm_enout(eerc, 0);
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for (i = 0; i < 100; i++)
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udelay(1000);
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/* Set default configuration */
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adm_enout((__u8)(eesk | eedi), eesk);
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/* Keep RC high for at least 30ms */
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adm_enout(eerc, eerc);
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for (i = 0; i < 30; i++)
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udelay(1000);
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/* Leave RC high and disable GPIO outputs */
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adm_disout((__u8)(eecs | eesk | eedi));
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}
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/* set up initial configuration for cpu port */
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cfg = (0x8000 | /* Auto MDIX */
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(0xf << 10) | /* PVID */
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(1 << 4) | /* Tagging */
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0xf); /* full duplex, 100Mbps, auto neg, flow ctrl */
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adm_wreg(port_conf[5], cfg);
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/* vlan mode select register (0x11): vlan on, mac clone */
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adm_wreg(0x11, 0xff30);
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return 0;
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}
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static int handle_registers(void *driver, char *buf, int nr)
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{
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int i, len = 0;
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for (i = 0; i <= 0x33; i++) {
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len += sprintf(buf + len, "0x%02x: 0x%04x\n", i, adm_rreg(0, i));
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}
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return len;
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}
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static int handle_counters(void *driver, char *buf, int nr)
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{
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int i, len = 0;
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for (i = 0; i <= 0x3c; i++) {
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len += sprintf(buf + len, "0x%02x: 0x%08x\n", i, adm_rreg(1, i));
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}
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return len;
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}
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static int detect_adm(void)
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{
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int ret = 0;
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#ifdef CONFIG_BCM47XX
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char buf[20];
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int boardflags = 0;
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int boardnum = 0;
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if (nvram_getenv("boardflags", buf, sizeof(buf)) >= 0)
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boardflags = simple_strtoul(buf, NULL, 0);
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if (nvram_getenv("boardnum", buf, sizeof(buf)) >= 0)
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boardnum = simple_strtoul(buf, NULL, 0);
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if ((boardnum == 44) && (boardflags == 0x0388)) { /* Trendware TEW-411BRP+ */
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ret = 1;
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eecs = get_gpiopin("adm_eecs", 2);
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eesk = get_gpiopin("adm_eesk", 3);
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eedi = get_gpiopin("adm_eedi", 4);
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eerc = get_gpiopin("adm_rc", 5);
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} else if ((boardflags & 0x80) || force) {
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ret = 1;
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eecs = get_gpiopin("adm_eecs", 2);
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eesk = get_gpiopin("adm_eesk", 3);
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eedi = get_gpiopin("adm_eedi", 4);
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eerc = get_gpiopin("adm_rc", 0);
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} else if (nvram_getenv("boardtype", buf, sizeof(buf)) >= 0) {
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if (strcmp(buf, "bcm94710dev") == 0) {
|
|
if (nvram_getenv("boardnum", buf, sizeof(buf)) >= 0) {
|
|
if (strncmp(buf, "42", 2) == 0) {
|
|
/* WRT54G v1.1 hack */
|
|
eecs = 2;
|
|
eesk = 3;
|
|
eedi = 5;
|
|
|
|
ret = 1;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (eecs)
|
|
eecs = (1 << eecs);
|
|
if (eesk)
|
|
eesk = (1 << eesk);
|
|
if (eedi)
|
|
eedi = (1 << eedi);
|
|
if (eerc)
|
|
eerc = (1 << eerc);
|
|
#else
|
|
ret = 1;
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int __init adm_init(void)
|
|
{
|
|
switch_config cfg[] = {
|
|
{"registers", handle_registers, NULL},
|
|
{"counters", handle_counters, NULL},
|
|
{"reset", NULL, handle_reset},
|
|
{"enable_vlan", handle_vlan_enable_read, handle_vlan_enable_write},
|
|
{NULL, NULL, NULL}
|
|
};
|
|
switch_config port[] = {
|
|
{"enable", handle_port_enable_read, handle_port_enable_write},
|
|
{"media", handle_port_media_read, handle_port_media_write},
|
|
{NULL, NULL, NULL}
|
|
};
|
|
switch_config vlan[] = {
|
|
{"ports", handle_vlan_port_read, handle_vlan_port_write},
|
|
{NULL, NULL, NULL}
|
|
};
|
|
switch_driver driver = {
|
|
name: DRIVER_NAME,
|
|
version: DRIVER_VERSION,
|
|
interface: "eth0",
|
|
ports: 6,
|
|
cpuport: 5,
|
|
vlans: 16,
|
|
driver_handlers: cfg,
|
|
port_handlers: port,
|
|
vlan_handlers: vlan,
|
|
};
|
|
|
|
if (!detect_adm())
|
|
return -ENODEV;
|
|
|
|
return switch_register_driver(&driver);
|
|
}
|
|
|
|
static void __exit adm_exit(void)
|
|
{
|
|
switch_unregister_driver(DRIVER_NAME);
|
|
}
|
|
|
|
|
|
module_init(adm_init);
|
|
module_exit(adm_exit);
|