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223 lines
6.0 KiB
Diff
223 lines
6.0 KiB
Diff
From 06384c65ff1a351b024c19d4bc0febaf8fcead5d Mon Sep 17 00:00:00 2001
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From: popcornmix <popcornmix@gmail.com>
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Date: Fri, 20 Jun 2014 17:19:27 +0100
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Subject: [PATCH 054/171] bcm2709: Simplify and strip down IRQ handler
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---
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arch/arm/include/asm/entry-macro-multi.S | 2 +
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arch/arm/mach-bcm2709/include/mach/entry-macro.S | 173 +++++++++++------------
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2 files changed, 87 insertions(+), 88 deletions(-)
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--- a/arch/arm/include/asm/entry-macro-multi.S
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+++ b/arch/arm/include/asm/entry-macro-multi.S
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@@ -1,5 +1,6 @@
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#include <asm/assembler.h>
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+#ifndef CONFIG_ARCH_BCM2709
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/*
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* Interrupt handling. Preserves r7, r8, r9
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*/
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@@ -28,6 +29,7 @@
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#endif
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9997:
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.endm
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+#endif
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.macro arch_irq_handler, symbol_name
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.align 5
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--- a/arch/arm/mach-bcm2709/include/mach/entry-macro.S
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+++ b/arch/arm/mach-bcm2709/include/mach/entry-macro.S
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@@ -22,102 +22,99 @@
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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- .macro disable_fiq
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- .endm
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+ .macro arch_ret_to_user, tmp1, tmp2
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+ .endm
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- .macro get_irqnr_preamble, base, tmp
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- ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
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- .endm
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-
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- .macro arch_ret_to_user, tmp1, tmp2
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- .endm
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-
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- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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- /* get core number */
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- mrc p15, 0, \tmp, c0, c0, 5
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- ubfx \tmp, \tmp, #0, #2
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-
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- /* get core's local interrupt controller */
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- ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source
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- add \irqstat, \irqstat, \tmp, lsl #2
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- ldr \tmp, [\irqstat]
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- /* ignore gpu interrupt */
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- bic \tmp, #0x100
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- /* ignore mailbox interrupts */
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- bics \tmp, #0xf0
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- beq 1005f
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-
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- @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
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- @ N.B. CLZ is an ARM5 instruction.
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- mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31)
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- sub \irqstat, \tmp, #1
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- eor \irqstat, \irqstat, \tmp
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- clz \tmp, \irqstat
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- sub \irqnr, \tmp
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- b 1020f
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-1005:
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- /* get core number */
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- mrc p15, 0, \tmp, c0, c0, 5
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- ubfx \tmp, \tmp, #0, #2
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-
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- cmp \tmp, #1
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- beq 1020f
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- cmp \tmp, #2
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- beq 1020f
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- cmp \tmp, #3
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- beq 1020f
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-
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- /* get masked status */
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- ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
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- mov \irqnr, #(ARM_IRQ0_BASE + 31)
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- and \tmp, \irqstat, #0x300 @ save bits 8 and 9
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- /* clear bits 8 and 9, and test */
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- bics \irqstat, \irqstat, #0x300
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- bne 1010f
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-
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- tst \tmp, #0x100
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- ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
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- movne \irqnr, #(ARM_IRQ1_BASE + 31)
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- @ Mask out the interrupts also present in PEND0 - see SW-5809
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- bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
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- bicne \irqstat, #((1<<18) | (1<<19))
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- bne 1010f
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-
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- tst \tmp, #0x200
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- ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
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- movne \irqnr, #(ARM_IRQ2_BASE + 31)
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- @ Mask out the interrupts also present in PEND0 - see SW-5809
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- bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
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- bicne \irqstat, #((1<<30))
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- beq 1020f
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+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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+ /* get core number */
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+ mrc p15, 0, \base, c0, c0, 5
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+ ubfx \base, \base, #0, #2
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+
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+ /* get core's local interrupt controller */
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+ ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source
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+ add \irqstat, \irqstat, \base, lsl #2
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+ ldr \tmp, [\irqstat]
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+#ifdef CONFIG_SMP
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+ /* test for mailbox0 (IPI) interrupt */
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+ tst \tmp, #0x10
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+ beq 1030f
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+
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+ /* get core's mailbox interrupt control */
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+ ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr
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+ add \irqstat, \irqstat, \base, lsl #4
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+ ldr \tmp, [\irqstat]
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+ clz \tmp, \tmp
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+ rsb \irqnr, \tmp, #31
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+ mov \tmp, #1
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+ lsl \tmp, \irqnr
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+ str \tmp, [\irqstat] @ clear interrupt source
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+ dsb
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+ mov r1, sp
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+ adr lr, BSYM(1b)
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+ b do_IPI
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+#endif
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+1030:
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+ /* check gpu interrupt */
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+ tst \tmp, #0x100
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+ beq 1040f
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+
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+ ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
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+ /* get masked status */
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+ ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
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+ mov \irqnr, #(ARM_IRQ0_BASE + 31)
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+ and \tmp, \irqstat, #0x300 @ save bits 8 and 9
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+ /* clear bits 8 and 9, and test */
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+ bics \irqstat, \irqstat, #0x300
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+ bne 1010f
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+
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+ tst \tmp, #0x100
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+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
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+ movne \irqnr, #(ARM_IRQ1_BASE + 31)
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+ @ Mask out the interrupts also present in PEND0 - see SW-5809
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+ bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
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+ bicne \irqstat, #((1<<18) | (1<<19))
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+ bne 1010f
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+
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+ tst \tmp, #0x200
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+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
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+ movne \irqnr, #(ARM_IRQ2_BASE + 31)
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+ @ Mask out the interrupts also present in PEND0 - see SW-5809
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+ bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
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+ bicne \irqstat, #((1<<30))
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+ beq 1020f
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1010:
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- @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
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- @ N.B. CLZ is an ARM5 instruction.
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- sub \tmp, \irqstat, #1
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- eor \irqstat, \irqstat, \tmp
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- clz \tmp, \irqstat
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- sub \irqnr, \tmp
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+ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
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+ sub \tmp, \irqstat, #1
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+ eor \irqstat, \irqstat, \tmp
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+ clz \tmp, \irqstat
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+ sub \irqnr, \tmp
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+ b 1050f
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+1040:
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+ cmp \tmp, #0
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+ beq 1020f
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+
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+ /* handle local (e.g. timer) interrupts */
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+ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
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+ mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31)
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+ sub \irqstat, \tmp, #1
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+ eor \irqstat, \irqstat, \tmp
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+ clz \tmp, \irqstat
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+ sub \irqnr, \tmp
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+1050:
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+ mov r1, sp
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+ @
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+ @ routine called with r0 = irq number, r1 = struct pt_regs *
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+ @
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+ adr lr, BSYM(1b)
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+ b asm_do_IRQ
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1020: @ EQ will be set if no irqs pending
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+ .endm
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- .endm
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-
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- .macro test_for_ipi, irqnr, irqstat, base, tmp
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- /* get core number */
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- mrc p15, 0, \tmp, c0, c0, 5
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- ubfx \tmp, \tmp, #0, #2
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- /* get core's mailbox interrupt control */
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- ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr
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- add \irqstat, \irqstat, \tmp, lsl #4
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- ldr \tmp, [\irqstat]
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- cmp \tmp, #0
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- beq 1030f
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- clz \tmp, \tmp
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- rsb \irqnr, \tmp, #31
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- mov \tmp, #1
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- lsl \tmp, \irqnr
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- str \tmp, [\irqstat] @ clear interrupt source
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- dsb
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-1030: @ EQ will be set if no irqs pending
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- .endm
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+/*
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+ * Interrupt handling. Preserves r7, r8, r9
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+ */
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+ .macro arch_irq_handler_default
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+1: get_irqnr_and_base r0, r2, r6, lr
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+ .endm
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