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225 lines
5.5 KiB
Diff
225 lines
5.5 KiB
Diff
--- a/arch/mips/ath79/gpio.c
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+++ b/arch/mips/ath79/gpio.c
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@@ -20,9 +20,14 @@
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/gpio.h>
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+#include <linux/irq.h>
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+#include <linux/interrupt.h>
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+
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+#include <linux/of.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79.h>
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+#include <asm/mach-ath79/irq.h>
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#include "common.h"
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void __iomem *ath79_gpio_base;
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@@ -31,6 +36,13 @@ EXPORT_SYMBOL_GPL(ath79_gpio_base);
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static unsigned long ath79_gpio_count;
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static DEFINE_SPINLOCK(ath79_gpio_lock);
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+/*
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+ * gpio_both_edge is a bitmask of which gpio pins need to have
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+ * the detect priority flipped from the interrupt handler to
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+ * emulate IRQ_TYPE_EDGE_BOTH.
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+ */
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+static unsigned long gpio_both_edge = 0;
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+
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static void __ath79_gpio_set_value(unsigned gpio, int value)
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{
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void __iomem *base = ath79_gpio_base;
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@@ -235,6 +247,132 @@ void __init ath79_gpio_output_select(uns
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spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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}
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+static int ath79_gpio_irq_type(struct irq_data *d, unsigned type)
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+{
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+ int offset = d->irq - ATH79_GPIO_IRQ_BASE;
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+ void __iomem *base = ath79_gpio_base;
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+ unsigned long flags;
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+ unsigned long int_type;
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+ unsigned long int_polarity;
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+ unsigned long bit = (1 << offset);
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+
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+ spin_lock_irqsave(&ath79_gpio_lock, flags);
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+
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+ int_type = __raw_readl(base + AR71XX_GPIO_REG_INT_TYPE);
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+ int_polarity = __raw_readl(base + AR71XX_GPIO_REG_INT_POLARITY);
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+
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+ gpio_both_edge &= ~bit;
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+
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+ switch (type) {
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+ case IRQ_TYPE_EDGE_RISING:
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+ int_type &= ~bit;
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+ int_polarity |= bit;
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+ break;
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+
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+ case IRQ_TYPE_EDGE_FALLING:
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+ int_type &= ~bit;
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+ int_polarity &= ~bit;
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+ break;
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+
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+ case IRQ_TYPE_LEVEL_HIGH:
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+ int_type |= bit;
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+ int_polarity |= bit;
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+ break;
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+
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+ case IRQ_TYPE_LEVEL_LOW:
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+ int_type |= bit;
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+ int_polarity &= ~bit;
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+ break;
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+
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+ case IRQ_TYPE_EDGE_BOTH:
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+ int_type |= bit;
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+ /* set polarity based on current value */
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+ if (gpio_get_value(offset)) {
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+ int_polarity &= ~bit;
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+ } else {
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+ int_polarity |= bit;
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+ }
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+ /* flip this gpio in the interrupt handler */
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+ gpio_both_edge |= bit;
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+ break;
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+
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+ default:
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+ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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+ return -EINVAL;
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+ }
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+
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+ __raw_writel(int_type, base + AR71XX_GPIO_REG_INT_TYPE);
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+ __raw_writel(int_polarity, base + AR71XX_GPIO_REG_INT_POLARITY);
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+
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+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_MODE) | (1 << offset),
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+ base + AR71XX_GPIO_REG_INT_MODE);
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+
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+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) & ~(1 << offset),
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+ base + AR71XX_GPIO_REG_INT_ENABLE);
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+
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+ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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+ return 0;
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+}
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+
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+static void ath79_gpio_irq_enable(struct irq_data *d)
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+{
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+ int offset = d->irq - ATH79_GPIO_IRQ_BASE;
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+ void __iomem *base = ath79_gpio_base;
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+
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+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) | (1 << offset),
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+ base + AR71XX_GPIO_REG_INT_ENABLE);
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+}
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+
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+static void ath79_gpio_irq_disable(struct irq_data *d)
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+{
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+ int offset = d->irq - ATH79_GPIO_IRQ_BASE;
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+ void __iomem *base = ath79_gpio_base;
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+
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+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_ENABLE) & ~(1 << offset),
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+ base + AR71XX_GPIO_REG_INT_ENABLE);
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+}
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+
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+static struct irq_chip ath79_gpio_irqchip = {
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+ .name = "GPIO",
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+ .irq_enable = ath79_gpio_irq_enable,
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+ .irq_disable = ath79_gpio_irq_disable,
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+ .irq_set_type = ath79_gpio_irq_type,
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+};
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+
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+static irqreturn_t ath79_gpio_irq(int irq, void *dev)
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+{
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+ void __iomem *base = ath79_gpio_base;
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+ unsigned long stat = __raw_readl(base + AR71XX_GPIO_REG_INT_PENDING);
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+ int bit_num;
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+
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+ for_each_set_bit(bit_num, &stat, sizeof(stat) * BITS_PER_BYTE) {
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+ unsigned long bit = BIT(bit_num);
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+
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+ if (bit & gpio_both_edge) {
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+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_INT_POLARITY) ^ bit,
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+ base + AR71XX_GPIO_REG_INT_POLARITY);
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+ }
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+
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+ generic_handle_irq(ATH79_GPIO_IRQ(bit_num));
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+ }
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static int __init ath79_gpio_irq_init(struct gpio_chip *chip)
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+{
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+ int irq;
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+ int irq_base = ATH79_GPIO_IRQ_BASE;
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+
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+ for (irq = irq_base; irq < irq_base + chip->ngpio; irq++) {
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+ irq_set_chip_data(irq, chip);
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+ irq_set_chip_and_handler(irq, &ath79_gpio_irqchip, handle_simple_irq);
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+ irq_set_noprobe(irq);
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+ }
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+
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+ return 0;
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+}
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+
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void __init ath79_gpio_init(void)
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{
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int err;
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@@ -271,6 +409,10 @@ void __init ath79_gpio_init(void)
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err = gpiochip_add(&ath79_gpio_chip);
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if (err)
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panic("cannot add AR71xx GPIO chip, error=%d", err);
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+
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+ ath79_gpio_irq_init(&ath79_gpio_chip);
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+
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+ request_irq(ATH79_MISC_IRQ(2), ath79_gpio_irq, 0, "ath79-gpio", NULL);
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}
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int gpio_get_value(unsigned gpio)
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@@ -293,14 +435,22 @@ EXPORT_SYMBOL(gpio_set_value);
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int gpio_to_irq(unsigned gpio)
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{
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- /* FIXME */
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- return -EINVAL;
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+ if (gpio > ath79_gpio_count) {
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+ return -EINVAL;
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+ }
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+
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+ return ATH79_GPIO_IRQ_BASE + gpio;
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}
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EXPORT_SYMBOL(gpio_to_irq);
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int irq_to_gpio(unsigned irq)
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{
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- /* FIXME */
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- return -EINVAL;
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+ unsigned gpio = irq - ATH79_GPIO_IRQ_BASE;
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+
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+ if (gpio > ath79_gpio_count) {
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+ return -EINVAL;
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+ }
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+
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+ return gpio;
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}
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EXPORT_SYMBOL(irq_to_gpio);
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--- a/arch/mips/include/asm/mach-ath79/irq.h
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+++ b/arch/mips/include/asm/mach-ath79/irq.h
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@@ -10,7 +10,7 @@
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#define __ASM_MACH_ATH79_IRQ_H
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#define MIPS_CPU_IRQ_BASE 0
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-#define NR_IRQS 51
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+#define NR_IRQS 83
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#define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x))
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@@ -30,6 +30,10 @@
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#define ATH79_IP3_IRQ_COUNT 3
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#define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x))
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+#define ATH79_GPIO_IRQ_BASE (ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT)
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+#define ATH79_GPIO_IRQ_COUNT 32
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+#define ATH79_GPIO_IRQ(_x) (ATH79_GPIO_IRQ_BASE + (_x))
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+
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#include_next <irq.h>
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#endif /* __ASM_MACH_ATH79_IRQ_H */
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