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482 lines
12 KiB
Diff
482 lines
12 KiB
Diff
From 4b27423676485d05bcd6fc6f3809164fb8f9d22d Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Sat, 12 Nov 2011 12:19:55 +0100
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Subject: [PATCH 30/60] SPI: MIPS: BCM63XX: Add HSSPI driver
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Add a driver for the High Speed SPI controller found on newer BCM63XX SoCs.
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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.../include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h | 2 +
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drivers/spi/Kconfig | 7 +
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drivers/spi/Makefile | 1 +
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drivers/spi/spi-bcm63xx-hsspi.c | 427 ++++++++++++++++++++
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4 files changed, 437 insertions(+), 0 deletions(-)
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create mode 100644 drivers/spi/spi-bcm63xx-hsspi.c
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
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@@ -18,4 +18,6 @@ struct bcm63xx_hsspi_pdata {
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#define HSSPI_PLL_HZ_6328 133333333
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#define HSSPI_PLL_HZ_6362 400000000
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+#define HSSPI_BUFFER_LEN 512
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+
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#endif /* BCM63XX_DEV_HSSPI_H */
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--- a/drivers/spi/Kconfig
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+++ b/drivers/spi/Kconfig
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@@ -112,6 +112,13 @@ config SPI_BCM63XX
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help
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Enable support for the SPI controller on the Broadcom BCM63xx SoCs.
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+config SPI_BCM63XX_HSSPI
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+ tristate "Broadcom BCM63XX HS SPI controller driver"
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+ depends on BCM63XX
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+ help
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+ This enables support for the High Speed SPI controller present on
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+ newer Broadcom BCM63XX SoCs.
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+
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config SPI_BITBANG
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tristate "Utilities for Bitbanging SPI masters"
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help
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--- a/drivers/spi/Makefile
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+++ b/drivers/spi/Makefile
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@@ -16,6 +16,7 @@ obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
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obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
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obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o
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obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
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+obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
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obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
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obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
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obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
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--- /dev/null
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+++ b/drivers/spi/spi-bcm63xx-hsspi.c
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@@ -0,0 +1,427 @@
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+/*
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+ * Broadcom BCM63XX High Speed SPI Controller driver
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+ *
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+ * Copyright 2000-2010 Broadcom Corporation
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+ * Copyright 2012 Jonas Gorski <jonas.gorski@gmail.com>
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+ *
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+ * Licensed under the GNU/GPL. See COPYING for details.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/io.h>
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+#include <linux/clk.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/delay.h>
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+#include <linux/dma-mapping.h>
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+#include <linux/err.h>
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+#include <linux/interrupt.h>
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+#include <linux/spi/spi.h>
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+#include <linux/workqueue.h>
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+
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+#include <bcm63xx_regs.h>
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+#include <bcm63xx_dev_hsspi.h>
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+
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+#define HSSPI_OP_CODE_SHIFT 13
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+#define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT)
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+#define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT)
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+#define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT)
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+#define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT)
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+
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+#define HSSPI_MAX_PREPEND_LEN 15
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+
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+#define HSSPI_MAX_SYNC_CLOCK 30000000
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+
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+struct bcm63xx_hsspi {
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+ struct completion done;
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+ struct spi_transfer *curr_trans;
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+
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+ struct platform_device *pdev;
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+ struct clk *clk;
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+ void __iomem *regs;
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+ u8 __iomem *fifo;
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+
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+ u32 speed_hz;
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+ int irq;
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+};
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+
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+static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs, int hz,
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+ int profile)
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+{
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+ u32 reg;
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+
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+ reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
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+ bcm_hsspi_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
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+ HSSPI_PROFILE_CLK_CTRL_REG(profile));
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+
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+ reg = bcm_hsspi_readl(HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
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+ if (hz > HSSPI_MAX_SYNC_CLOCK)
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+ reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
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+ else
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+ reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
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+ bcm_hsspi_writel(reg, HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
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+}
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+
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+static int bcm63xx_hsspi_do_txrx(struct spi_device *spi,
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+ struct spi_transfer *t1,
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+ struct spi_transfer *t2)
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+{
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+ struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
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+ u8 chip_select = spi->chip_select;
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+ u16 opcode = 0;
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+ int len, prepend_size = 0;
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+
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+ init_completion(&bs->done);
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+
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+ bs->curr_trans = t2 ? t2 : t1;
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+ bcm63xx_hsspi_set_clk(bs, bs->curr_trans->speed_hz, chip_select);
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+
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+ if (t2 && !t2->tx_buf)
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+ prepend_size = t1->len;
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+
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+ bcm_hsspi_writel(prepend_size << MODE_CTRL_PREPENDBYTE_CNT_SHIFT |
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+ 2 << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT |
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+ 2 << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT | 0xff,
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+ HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
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+
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+ if (t1->rx_buf && t1->tx_buf)
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+ opcode = HSSPI_OP_READ_WRITE;
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+ else if (t1->rx_buf || (t2 && t2->rx_buf))
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+ opcode = HSSPI_OP_READ;
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+ else if (t1->tx_buf)
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+ opcode = HSSPI_OP_WRITE;
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+
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+ if (opcode == HSSPI_OP_READ && t2)
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+ len = t2->len;
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+ else
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+ len = t1->len;
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+
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+ if (t1->tx_buf) {
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+ memcpy_toio(bs->fifo + 2, t1->tx_buf, t1->len);
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+ if (t2 && t2->tx_buf) {
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+ memcpy_toio(bs->fifo + 2 + t1->len,
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+ t2->tx_buf, t2->len);
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+ len += t2->len;
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+ }
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+ }
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+
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+ opcode |= len;
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+ memcpy_toio(bs->fifo, &opcode, sizeof(opcode));
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+
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+ /* enable interrupt */
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+ bcm_hsspi_writel(HSSPI_PING0_CMD_DONE, HSSPI_INT_MASK_REG);
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+
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+ /* start the transfer */
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+ bcm_hsspi_writel(chip_select << PINGPONG_CMD_SS_SHIFT |
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+ chip_select << PINGPONG_CMD_PROFILE_SHIFT |
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+ PINGPONG_COMMAND_START_NOW,
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+ HSSPI_PINGPONG_COMMAND_REG(0));
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+
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+ if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
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+ dev_err(&bs->pdev->dev, "transfer timed out!\n");
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+ return -ETIMEDOUT;
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+ }
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+
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+ return t1->len + (t2 ? t2->len : 0);
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+}
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+
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+static int bcm63xx_hsspi_setup(struct spi_device *spi)
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+{
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+ u32 reg;
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+
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+ if (spi->bits_per_word != 8)
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+ return -EINVAL;
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+
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+ if (spi->max_speed_hz == 0)
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+ return -EINVAL;
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+
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+ reg = bcm_hsspi_readl(HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
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+ reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
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+ if (spi->mode & SPI_CPHA)
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+ reg |= SIGNAL_CTRL_LAUNCH_RISING;
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+ else
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+ reg |= SIGNAL_CTRL_LATCH_RISING;
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+ bcm_hsspi_writel(reg, HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
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+
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+ return 0;
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+}
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+
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+static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
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+ struct spi_message *msg)
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+{
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+ struct spi_transfer *t, *prev = NULL;
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+ struct spi_device *spi = msg->spi;
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+ u32 reg;
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+ int ret = -EINVAL;
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+ int len = 0;
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+
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+ /* check if we are able to make these transfers */
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+ list_for_each_entry(t, &msg->transfers, transfer_list) {
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+ if (!t->tx_buf && !t->rx_buf)
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+ goto out;
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+
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+ if (t->speed_hz == 0)
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+ t->speed_hz = spi->max_speed_hz;
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+
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+ if (t->speed_hz > spi->max_speed_hz)
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+ goto out;
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+
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+ if (t->len > HSSPI_BUFFER_LEN)
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+ goto out;
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+
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+ /*
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+ * This controller does not support keeping the chip select
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+ * active between transfers.
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+ * This logic currently supports combining:
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+ * write then read with no cs_change (e.g. m25p80 RDSR)
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+ * write then write with no cs_change (e.g. m25p80 PP)
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+ */
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+ if (prev && prev->tx_buf && !prev->cs_change && !t->cs_change) {
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+ /*
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+ * reject if we have to combine two tx transfers and
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+ * their combined length is bigger than the buffer
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+ */
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+ if (prev->tx_buf && t->tx_buf &&
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+ (prev->len + t->len) > HSSPI_BUFFER_LEN)
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+ goto out;
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+ /*
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+ * reject if we need write more than 15 bytes in read
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+ * then write.
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+ */
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+ if (prev->tx_buf && t->rx_buf &&
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+ prev->len > HSSPI_MAX_PREPEND_LEN)
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+ goto out;
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+ }
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+
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+ }
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+
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+ /* setup clock polarity */
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+ reg = bcm_hsspi_readl(HSSPI_GLOBAL_CTRL_REG);
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+ reg &= ~GLOBAL_CTRL_CLK_POLARITY;
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+ if (spi->mode & SPI_CPOL)
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+ reg |= GLOBAL_CTRL_CLK_POLARITY;
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+ bcm_hsspi_writel(reg, HSSPI_GLOBAL_CTRL_REG);
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+
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+ list_for_each_entry(t, &msg->transfers, transfer_list) {
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+ if (prev && prev->tx_buf && !prev->cs_change && !t->cs_change) {
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+ /* combine write with following transfer */
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+ ret = bcm63xx_hsspi_do_txrx(msg->spi, prev, t);
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+ if (ret < 0)
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+ goto out;
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+
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+ len += ret;
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+ prev = NULL;
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+ continue;
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+ }
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+
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+ /* write the previous pending transfer */
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+ if (prev != NULL) {
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+ ret = bcm63xx_hsspi_do_txrx(msg->spi, prev, NULL);
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+ if (ret < 0)
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+ goto out;
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+
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+ len += ret;
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+ }
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+
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+ prev = t;
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+ }
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+
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+ /* do last pending transfer */
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+ if (prev != NULL) {
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+ ret = bcm63xx_hsspi_do_txrx(msg->spi, prev, NULL);
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+ if (ret < 0)
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+ goto out;
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+ len += ret;
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+ }
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+
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+ msg->actual_length = len;
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+ ret = 0;
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+out:
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+ msg->status = ret;
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+ spi_finalize_current_message(master);
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+ return 0;
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+}
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+
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+static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
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+{
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+ struct spi_master *master = (struct spi_master *)dev_id;
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+ struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
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+
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+ if (bcm_hsspi_readl(HSSPI_INT_STATUS_MASKED_REG) == 0)
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+ return IRQ_NONE;
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+
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+ bcm_hsspi_writel(HSSPI_INT_CLEAR_ALL, HSSPI_INT_STATUS_REG);
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+ bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
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+
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+ if (bs->curr_trans && bs->curr_trans->rx_buf)
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+ memcpy_fromio(bs->curr_trans->rx_buf, bs->fifo,
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+ bs->curr_trans->len);
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+ complete(&bs->done);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static int bcm63xx_hsspi_probe(struct platform_device *pdev)
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+{
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+
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+ struct spi_master *master;
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+ struct bcm63xx_hsspi *bs;
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+ struct resource *res_mem;
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+ void __iomem *regs;
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+ struct device *dev = &pdev->dev;
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+ struct bcm63xx_hsspi_pdata *pdata = pdev->dev.platform_data;
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+ struct clk *clk;
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+ int irq;
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+ int ret;
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+
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+ irq = platform_get_irq(pdev, 0);
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+ if (irq < 0) {
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+ dev_err(dev, "no irq\n");
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+ return -ENXIO;
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+ }
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+
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+ res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ regs = devm_request_and_ioremap(dev, res_mem);
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+ if (!regs) {
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+ dev_err(dev, "unable to ioremap regs\n");
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+ return -ENXIO;
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+ }
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+
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+ clk = clk_get(dev, "hsspi");
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+
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+ if (IS_ERR(clk)) {
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+ ret = PTR_ERR(clk);
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+ goto out_release;
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+ }
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+
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+ clk_prepare_enable(clk);
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+
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+ master = spi_alloc_master(&pdev->dev, sizeof(*bs));
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+ if (!master) {
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+ ret = -ENOMEM;
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+ goto out_disable_clk;
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+ }
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+
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+ bs = spi_master_get_devdata(master);
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+ bs->pdev = pdev;
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+ bs->clk = clk;
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+ bs->regs = regs;
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+
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+ master->bus_num = pdata->bus_num;
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+ master->num_chipselect = 8;
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+ master->setup = bcm63xx_hsspi_setup;
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+ master->transfer_one_message = bcm63xx_hsspi_transfer_one;
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+ master->mode_bits = SPI_CPOL | SPI_CPHA;
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+
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+ bs->speed_hz = pdata->speed_hz;
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+ bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
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+
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+ platform_set_drvdata(pdev, master);
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+
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+ bs->curr_trans = NULL;
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+
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+ /* Initialize the hardware */
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+ bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
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+
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+ /* clean up any pending interrupts */
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+ bcm_hsspi_writel(HSSPI_INT_CLEAR_ALL, HSSPI_INT_STATUS_REG);
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+
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+ bcm_hsspi_writel(bcm_hsspi_readl(HSSPI_GLOBAL_CTRL_REG) |
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+ GLOBAL_CTRL_CLK_GATE_SSOFF,
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+ HSSPI_GLOBAL_CTRL_REG);
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+
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+ ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
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+ pdev->name, master);
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+
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+ if (ret)
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+ goto out_put_master;
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+
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+ /* register and we are done */
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+ ret = spi_register_master(master);
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+ if (ret)
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+ goto out_free_irq;
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+
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+ return 0;
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+
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+out_free_irq:
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+ devm_free_irq(dev, bs->irq, master);
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+out_put_master:
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+ spi_master_put(master);
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+out_disable_clk:
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+ clk_disable_unprepare(clk);
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+ clk_put(clk);
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+out_release:
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+ devm_ioremap_release(dev, regs);
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+
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+ return ret;
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+}
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+
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+
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+static int __exit bcm63xx_hsspi_remove(struct platform_device *pdev)
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+{
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+ struct spi_master *master = platform_get_drvdata(pdev);
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+ struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
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+
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+ spi_unregister_master(master);
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+
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+ /* reset the hardware and block queue progress */
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+ bcm_hsspi_writel(0, HSSPI_INT_MASK_REG);
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+ clk_disable_unprepare(bs->clk);
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+ clk_put(bs->clk);
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+
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+ return 0;
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+}
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+
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+#ifdef CONFIG_PM
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+static int bcm63xx_hsspi_suspend(struct platform_device *pdev,
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+ pm_message_t mesg)
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+{
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+ struct spi_master *master = platform_get_drvdata(pdev);
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+ struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
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+
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+ spi_master_suspend(master);
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+ clk_disable(bs->clk);
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+
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+ return 0;
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+}
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+
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+static int bcm63xx_hsspi_resume(struct platform_device *pdev)
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+{
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+ struct spi_master *master = platform_get_drvdata(pdev);
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+ struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
|
|
+
|
|
+ clk_enable(bs->clk);
|
|
+ spi_master_resume(master);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct dev_pm_ops bcm63xx_hsspi_pm_ops = {
|
|
+ .suspend = bcm63xx_hsspi_suspend,
|
|
+ .resume = bcm63xx_hsspi_resume,
|
|
+};
|
|
+
|
|
+#define BCM63XX_HSSPI_PM_OPS (&bcm63xx_hsspi_pm_ops)
|
|
+#else
|
|
+#define BCM63XX_HSSPI_PM_OPS NULL
|
|
+#endif
|
|
+
|
|
+
|
|
+
|
|
+static struct platform_driver bcm63xx_hsspi_driver = {
|
|
+ .driver = {
|
|
+ .name = "bcm63xx-hsspi",
|
|
+ .owner = THIS_MODULE,
|
|
+ .pm = BCM63XX_HSSPI_PM_OPS,
|
|
+ },
|
|
+ .probe = bcm63xx_hsspi_probe,
|
|
+ .remove = __exit_p(bcm63xx_hsspi_remove),
|
|
+};
|
|
+
|
|
+module_platform_driver(bcm63xx_hsspi_driver);
|
|
+
|
|
+MODULE_ALIAS("platform:bcm63xx_hsspi");
|
|
+MODULE_DESCRIPTION("Broadcom BCM63xx HS SPI Controller driver");
|
|
+MODULE_AUTHOR("Jonas Gorski <jonas.gorski@gmail.com>");
|
|
+MODULE_LICENSE("GPL");
|