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258 lines
5.9 KiB
C
258 lines
5.9 KiB
C
/*****************************************************************************
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* DANUBE BootROM
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* Copyright (c) 2005, Infineon Technologies AG, All rights reserved
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* IFAP DC COM SD
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*****************************************************************************/
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#include <config.h>
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//#include <lib.h>
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#include <asm/danube.h>
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#include <asm/addrspace.h>
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#include <asm/ifx_asc.h>
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#define ASC_FIFO_PRESENT
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#define SET_BIT(reg, mask) reg |= (mask)
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#define CLEAR_BIT(reg, mask) reg &= (~mask)
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#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
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#define SET_BITS(reg, mask) SET_BIT(reg, mask)
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#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
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typedef unsigned char u8;
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typedef unsigned short u16;
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typedef unsigned long u32;
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typedef signed long s32;
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typedef unsigned int uint;
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typedef unsigned long ulong;
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typedef volatile unsigned short vuint;
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void serial_setbrg (void);
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/*TODO: undefine this !!!*/
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#undef DEBUG_ASC_RAW
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#ifdef DEBUG_ASC_RAW
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#define DEBUG_ASC_RAW_RX_BUF 0xA0800000
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#define DEBUG_ASC_RAW_TX_BUF 0xA0900000
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#endif
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static volatile DanubeAsc_t *pAsc = (DanubeAsc_t *)DANUBE_ASC1;
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typedef struct{
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u16 fdv; /* 0~511 fractional divider value*/
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u16 reload; /* 13 bit reload value*/
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} ifx_asc_baud_reg_t;
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#ifdef ON_VENUS
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/*9600 @1.25M rel 00.08*/
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//#define FDV 503
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//#define RELOAD 7
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/*9600 @0.625M rel final00.01 & rtl_freeze*/
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#define FDV 503
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#define RELOAD 3
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/* first index is DDR_SEL, second index is FPI_SEL */
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#endif
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static ifx_asc_baud_reg_t g_danube_asc_baud[4][2] =
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{
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#ifdef ON_VENUS
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{{503,3},{503,3}}, /* 1152000 @ 166.67M and half*/
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{{503,3},{503,3}}, /* 1152000 @ 133.3M and half*/
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{{503,3},{503,3}}, /* 1152000 @ 111.11M and half*/
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{{503.3},{503,3}} /* 1152000 @ 83.33M and half*/
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#else
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/* TAPEOUT table */
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{{436,76},{419,36}}, /* 1152000 @ 166.67M and half*/
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{{453,63},{453,31}}, /* 1152000 @ 133.3M and half*/
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{{501,58},{510,29}}, /* 1152000 @ 111.11M and half*/
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{{419.36},{453,19}} /* 1152000 @ 83.33M and half*/
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#endif
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};
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/******************************************************************************
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*
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* asc_init - initialize a Danube ASC channel
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*
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* This routine initializes the number of data bits, parity
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* and set the selected baud rate. Interrupts are disabled.
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* Set the modem control signals if the option is selected.
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*
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* RETURNS: N/A
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*/
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int serial_init (void)
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{
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/* and we have to set CLC register*/
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CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
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SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
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/* initialy we are in async mode */
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pAsc->asc_con = ASCCON_M_8ASYNC;
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/* select input port */
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pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
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/* TXFIFO's filling level */
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SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
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ASCTXFCON_TXFITLOFF, DANUBEASC_TXFIFO_FL);
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/* enable TXFIFO */
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SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
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/* RXFIFO's filling level */
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SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
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ASCRXFCON_RXFITLOFF, DANUBEASC_RXFIFO_FL);
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/* enable RXFIFO */
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SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
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/* set baud rate */
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serial_setbrg();
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/* enable error signals & Receiver enable */
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SET_BIT(pAsc->asc_whbstate, ASCWHBSTATE_SETREN|ASCCON_FEN|ASCCON_TOEN|ASCCON_ROEN);
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return 0;
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}
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void serial_setbrg (void)
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{
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u32 uiReloadValue, fdv;
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#if defined(ON_IKOS)
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/*1200 @77K */
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fdv=472;
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uiReloadValue=5;
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#else
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/*venus & tapeout */
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u32 ddr_sel,fpi_sel;
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ddr_sel = (* DANUBE_CGU_SYS) & 0x3;
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fpi_sel = ((* DANUBE_CGU_SYS) & 0x40)?1:0;
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fdv= g_danube_asc_baud[ddr_sel][fpi_sel].fdv;
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uiReloadValue=g_danube_asc_baud[ddr_sel][fpi_sel].reload;
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#endif //ON_IKOS
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/* Disable Baud Rate Generator; BG should only be written when R=0 */
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CLEAR_BIT(pAsc->asc_con, ASCCON_R);
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/* Enable Fractional Divider */
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SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */
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/* Set fractional divider value */
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pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK;
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/* Set reload value in BG */
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pAsc->asc_bg = uiReloadValue;
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/* Enable Baud Rate Generator */
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SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */
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}
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void serial_putc (const char c)
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{
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u32 txFl = 0;
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#ifdef DEBUG_ASC_RAW
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static u8 * debug = (u8 *) DEBUG_ASC_RAW_TX_BUF;
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*debug++=c;
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#endif
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if (c == '\n')
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serial_putc ('\r');
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/* check do we have a free space in the TX FIFO */
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/* get current filling level */
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do
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{
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txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
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}
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while ( txFl == DANUBEASC_TXFIFO_FULL );
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pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */
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/* check for errors */
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if ( pAsc->asc_state & ASCSTATE_TOE )
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{
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SET_BIT(pAsc->asc_whbstate, ASCWHBSTATE_CLRTOE);
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return;
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}
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}
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void serial_puts (const char *s)
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{
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while (*s)
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{
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serial_putc (*s++);
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}
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}
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int asc_inb(int timeout)
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{
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u32 symbol_mask;
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char c;
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while ((pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) {
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}
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symbol_mask = ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff);
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c = (char)(pAsc->asc_rbuf & symbol_mask);
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return (c);
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}
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int serial_getc (void)
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{
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char c;
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while ((pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 );
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c = (char)(pAsc->asc_rbuf & 0xff);
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#ifdef DEBUG_ASC_RAW
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static u8* debug=(u8*)(DEBUG_ASC_RAW_RX_BUF);
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*debug++=c;
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#endif
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return c;
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}
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int serial_tstc (void)
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{
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int res = 1;
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#ifdef ASC_FIFO_PRESENT
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if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
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{
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res = 0;
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}
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#else
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if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
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FBS_ISR_AR))
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{
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res = 0;
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}
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#endif
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#if 0
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else if ( pAsc->asc_con & ASCCON_FE )
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{
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SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
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res = 0;
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}
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else if ( pAsc->asc_con & ASCCON_PE )
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{
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SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
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res = 0;
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}
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else if ( pAsc->asc_con & ASCCON_OE )
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{
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SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
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res = 0;
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}
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#endif
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return res;
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}
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int serial_start(void)
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{
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return 1;
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}
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int serial_stop(void)
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{
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return 1;
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}
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