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123 lines
3.7 KiB
Diff
123 lines
3.7 KiB
Diff
From 16eb35ceea5b43e6f64c1a869721ea86c0da5260 Mon Sep 17 00:00:00 2001
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From: Yunhui Cui <yunhui.cui@nxp.com>
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Date: Thu, 25 Feb 2016 10:19:15 +0800
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Subject: [PATCH 106/113] mtd: fsl-quadspi: add DDR quad read for Spansion
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Add the DDR quad read support for the fsl-quadspi driver.
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And, add the Spansion s25fl128s NOR flash ddr quad mode
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support.
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Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
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---
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drivers/mtd/spi-nor/fsl-quadspi.c | 57 +++++++++++++++++++++++++++++++++++++
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1 file changed, 57 insertions(+)
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--- a/drivers/mtd/spi-nor/fsl-quadspi.c
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+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
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@@ -296,6 +296,7 @@ struct fsl_qspi {
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u32 nor_size;
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u32 nor_num;
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u32 clk_rate;
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+ u32 ddr_smp;
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unsigned int chip_base_addr; /* We may support two chips. */
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bool has_second_chip;
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bool big_endian;
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@@ -423,6 +424,19 @@ static void fsl_qspi_init_lut(struct fsl
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qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
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LUT1(FSL_READ, PAD4, rxfifo),
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base + QUADSPI_LUT(lut_base + 1));
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+ } else if (nor->flash_read == SPI_NOR_DDR_QUAD) {
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+ /* read mode : 1-4-4, such as Spansion s25fl128s. */
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+ qspi_writel(q, LUT0(CMD, PAD1, read_op)
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+ | LUT1(ADDR_DDR, PAD4, addrlen),
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+ base + QUADSPI_LUT(lut_base));
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+
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+ qspi_writel(q, LUT0(MODE_DDR, PAD4, 0xff)
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+ | LUT1(DUMMY, PAD1, read_dm),
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+ base + QUADSPI_LUT(lut_base + 1));
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+
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+ qspi_writel(q, LUT0(FSL_READ_DDR, PAD4, rxfifo)
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+ | LUT1(JMP_ON_CS, PAD1, 0),
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+ base + QUADSPI_LUT(lut_base + 2));
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}
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/* Write enable */
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@@ -534,6 +548,8 @@ static void fsl_qspi_init_lut(struct fsl
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static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
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{
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switch (cmd) {
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+ case SPINOR_OP_READ_1_4_4_D:
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+ case SPINOR_OP_READ4_1_4_4_D:
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case SPINOR_OP_READ4_1_1_4:
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case SPINOR_OP_READ_1_1_4:
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case SPINOR_OP_READ_FAST:
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@@ -736,6 +752,32 @@ static void fsl_qspi_set_map_addr(struct
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}
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/*
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+ * enable controller ddr quad mode to support different
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+ * vender flashes ddr quad mode.
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+ */
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+static void set_ddr_quad_mode(struct fsl_qspi *q)
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+{
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+ u32 reg, reg2;
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+
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+ reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
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+
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+ /* Firstly, disable the module */
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+ qspi_writel(q, reg | QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
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+
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+ /* Set the Sampling Register for DDR */
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+ reg2 = qspi_readl(q, q->iobase + QUADSPI_SMPR);
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+ reg2 &= ~QUADSPI_SMPR_DDRSMP_MASK;
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+ reg2 |= (((q->ddr_smp) << QUADSPI_SMPR_DDRSMP_SHIFT) &
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+ QUADSPI_SMPR_DDRSMP_MASK);
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+ qspi_writel(q, reg2, q->iobase + QUADSPI_SMPR);
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+
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+ /* Enable the module again (enable the DDR too) */
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+ reg |= QUADSPI_MCR_DDR_EN_MASK;
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+ qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
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+
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+}
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+
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+/*
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* There are two different ways to read out the data from the flash:
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* the "IP Command Read" and the "AHB Command Read".
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*
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@@ -775,6 +817,11 @@ static void fsl_qspi_init_abh_read(struc
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seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
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qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
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q->iobase + QUADSPI_BFGENCR);
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+
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+ /* enable the DDR quad read */
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+ if (q->nor->flash_read == SPI_NOR_DDR_QUAD)
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+ set_ddr_quad_mode(q);
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+
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}
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/* This function was used to prepare and enable QSPI clock */
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@@ -1108,6 +1155,12 @@ static int fsl_qspi_probe(struct platfor
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goto clk_failed;
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}
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+ /* find ddrsmp value */
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+ ret = of_property_read_u32(dev->of_node, "fsl,ddr-sampling-point",
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+ &q->ddr_smp);
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+ if (ret)
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+ q->ddr_smp = 0;
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+
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/* find the irq */
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ret = platform_get_irq(pdev, 0);
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if (ret < 0) {
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@@ -1164,6 +1217,10 @@ static int fsl_qspi_probe(struct platfor
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ret = of_property_read_bool(np, "m25p,fast-read");
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mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD;
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+ /* Can we enable the DDR Quad Read? */
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+ ret = of_property_read_bool(np, "ddr-quad-read");
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+ if (ret)
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+ mode = SPI_NOR_DDR_QUAD;
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ret = spi_nor_scan(nor, NULL, mode);
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if (ret)
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