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404 lines
12 KiB
Diff
404 lines
12 KiB
Diff
--- a/arch/mips/pci/Makefile
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+++ b/arch/mips/pci/Makefile
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@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
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obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
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ops-bcm63xx.o
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obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
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+obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o
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obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
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obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
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--- /dev/null
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+++ b/arch/mips/pci/pci-ar2315.c
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@@ -0,0 +1,345 @@
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+/*
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * as published by the Free Software Foundation; either version 2
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+ * of the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
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+ */
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+
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+/**
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+ * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
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+ * and interrupt. PCI interface supports MMIO access method, but does not
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+ * seem to support I/O ports.
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+ *
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+ * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
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+ * a memory read/write command on the PCI bus. 30 LSBs of address on
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+ * the bus are taken from memory read/write request and 2 MSBs are
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+ * determined by PCI unit configuration.
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+ *
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+ * To work with the configuration space instead of memory is necessary set
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+ * the CFG_SEL bit in the PCI_MISC_CONFIG register.
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+ *
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+ * Devices on the bus can perform DMA requests via chip BAR1. PCI host
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+ * controller BARs are programmend as if an external device is programmed.
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+ * Which means that during configuration, IDSEL pin of the chip should be
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+ * asserted.
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+ *
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+ * We know (and support) only one board that uses the PCI interface -
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+ * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
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+ * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
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+ * and IDSEL pin of AR125 is connected to AD[16] line.
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+ */
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+
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+#include <linux/types.h>
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+#include <linux/pci.h>
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+#include <linux/platform_device.h>
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/mm.h>
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+#include <linux/delay.h>
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+#include <linux/irq.h>
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+#include <linux/io.h>
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+#include <asm/paccess.h>
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+#include <ar231x_platform.h>
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+#include <ar231x.h>
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+#include <ar2315_regs.h>
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+
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+/* Arbitrary size of memory region to access the configuration space */
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+#define AR2315_PCI_CFG_SIZE 0x00100000
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+
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+#define AR2315_PCI_HOST_SLOT 3
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+#define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
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+
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+static void __iomem *ar2315_pci_cfg_mem;
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+
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+static int ar2315_pci_cfg_access(int devfn, int where, int size, u32 *ptr,
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+ bool write)
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+{
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+ int func = PCI_FUNC(devfn);
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+ int dev = PCI_SLOT(devfn);
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+ u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
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+ u32 mask = 0xffffffff >> 8 * (4 - size);
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+ u32 sh = (where & 3) * 8;
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+ u32 value, isr;
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+
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+ /* Prevent access past the remapped area */
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+ if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ /* Clear pending errors */
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+ ar231x_write_reg(AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
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+ /* Select Configuration access */
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+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
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+
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+ mb(); /* PCI must see space change before we begin */
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+
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+ value = __raw_readl(ar2315_pci_cfg_mem + addr);
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+
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+ isr = ar231x_read_reg(AR2315_PCI_ISR);
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+ if (isr & AR2315_PCI_INT_ABORT)
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+ goto exit_err;
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+
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+ if (write) {
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+ value = (value & ~(mask << sh)) | *ptr << sh;
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+ __raw_writel(value, ar2315_pci_cfg_mem + addr);
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+ isr = ar231x_read_reg(AR2315_PCI_ISR);
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+ if (isr & AR2315_PCI_INT_ABORT)
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+ goto exit_err;
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+ } else {
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+ *ptr = (value >> sh) & mask;
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+ }
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+
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+ goto exit;
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+
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+exit_err:
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+ ar231x_write_reg(AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
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+ if (!write)
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+ *ptr = 0xffffffff;
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+
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+exit:
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+ /* Select Memory access */
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+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
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+
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+ return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
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+ PCIBIOS_SUCCESSFUL;
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+}
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+
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+static inline int ar2315_pci_local_cfg_rd(unsigned devfn, int where, u32 *val)
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+{
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+ return ar2315_pci_cfg_access(devfn, where, sizeof(u32), val, false);
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+}
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+
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+static inline int ar2315_pci_local_cfg_wr(unsigned devfn, int where, u32 val)
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+{
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+ return ar2315_pci_cfg_access(devfn, where, sizeof(u32), &val, true);
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+}
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+
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+static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 *value)
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+{
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+ if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ return ar2315_pci_cfg_access(devfn, where, size, value, 0);
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+}
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+
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+static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 value)
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+{
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+ if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ return ar2315_pci_cfg_access(devfn, where, size, &value, 1);
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+}
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+
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+static struct pci_ops ar2315_pci_ops = {
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+ .read = ar2315_pci_cfg_read,
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+ .write = ar2315_pci_cfg_write,
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+};
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+
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+static struct resource ar2315_mem_resource = {
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+ .name = "ar2315-pci-mem",
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+ .start = AR2315_PCIEXT,
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+ .end = AR2315_PCIEXT + AR2315_PCIEXT_SZ - 1,
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+ .flags = IORESOURCE_MEM,
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+};
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+
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+/* PCI controller does not support I/O ports */
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+static struct resource ar2315_io_resource = {
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+ .name = "ar2315-pci-io",
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+ .start = 0,
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+ .end = 0,
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+ .flags = IORESOURCE_IO,
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+};
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+
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+static struct pci_controller ar2315_pci_controller = {
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+ .pci_ops = &ar2315_pci_ops,
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+ .mem_resource = &ar2315_mem_resource,
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+ .io_resource = &ar2315_io_resource,
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+ .mem_offset = 0x00000000UL,
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+ .io_offset = 0x00000000UL,
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+};
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+
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+static int ar2315_pci_host_setup(void)
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+{
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+ unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
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+ int res;
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+ u32 id;
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+
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+ res = ar2315_pci_local_cfg_rd(devfn, PCI_VENDOR_ID, &id);
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+ if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
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+ return -ENODEV;
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+
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+ /* Program MBARs */
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+ ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_0,
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+ AR2315_PCI_HOST_MBAR0);
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+ ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_1,
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+ AR2315_PCI_HOST_MBAR1);
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+ ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_2,
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+ AR2315_PCI_HOST_MBAR2);
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+
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+ /* Run */
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+ ar2315_pci_local_cfg_wr(devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
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+ PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
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+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
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+ PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
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+
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+ return 0;
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+}
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+
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+static void ar2315_pci_irq_handler(unsigned irq, struct irq_desc *desc)
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+{
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+ u32 pending = ar231x_read_reg(AR2315_PCI_ISR) &
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+ ar231x_read_reg(AR2315_PCI_IMR);
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+
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+ if (pending & AR2315_PCI_INT_EXT)
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+ generic_handle_irq(AR2315_PCI_IRQ_EXT);
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+ else if (pending & AR2315_PCI_INT_ABORT)
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+ generic_handle_irq(AR2315_PCI_IRQ_ABORT);
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+ else
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+ spurious_interrupt();
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+}
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+
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+static void ar2315_pci_irq_mask(struct irq_data *d)
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+{
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+ u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
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+
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+ ar231x_mask_reg(AR2315_PCI_IMR, m, 0);
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+}
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+
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+static void ar2315_pci_irq_mask_ack(struct irq_data *d)
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+{
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+ u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
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+
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+ ar231x_mask_reg(AR2315_PCI_IMR, m, 0);
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+ ar231x_write_reg(AR2315_PCI_ISR, m);
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+}
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+
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+static void ar2315_pci_irq_unmask(struct irq_data *d)
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+{
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+ u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
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+
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+ ar231x_mask_reg(AR2315_PCI_IMR, 0, m);
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+}
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+
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+static struct irq_chip ar2315_pci_irq_chip = {
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+ .name = "AR2315-PCI",
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+ .irq_mask = ar2315_pci_irq_mask,
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+ .irq_mask_ack = ar2315_pci_irq_mask_ack,
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+ .irq_unmask = ar2315_pci_irq_unmask,
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+};
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+
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+static void ar2315_pci_irq_init(void)
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+{
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+ int i;
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+
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+ ar231x_mask_reg(AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
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+ ar231x_mask_reg(AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
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+ AR2315_PCI_INT_EXT), 0);
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+
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+ for (i = 0; i < AR2315_PCI_IRQ_COUNT; ++i) {
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+ int irq = AR2315_PCI_IRQ_BASE + i;
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+
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+ irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip,
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+ handle_level_irq);
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+ }
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+
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+ irq_set_chained_handler(AR2315_IRQ_LCBUS_PCI, ar2315_pci_irq_handler);
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+
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+ /* Clear any pending Abort or external Interrupts
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+ * and enable interrupt processing */
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+ ar231x_write_reg(AR2315_PCI_ISR, (AR2315_PCI_INT_ABORT |
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+ AR2315_PCI_INT_EXT));
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+ ar231x_mask_reg(AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
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+}
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+
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+static int ar2315_pci_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ u32 reg;
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+ int res;
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+
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+ /* Remap PCI config space */
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+ ar2315_pci_cfg_mem = devm_ioremap_nocache(dev, AR2315_PCIEXT,
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+ AR2315_PCI_CFG_SIZE);
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+ if (!ar2315_pci_cfg_mem) {
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+ dev_err(dev, "failed to remap PCI config space\n");
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+ return -ENOMEM;
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+ }
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+
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+ /* Reset PCI DMA logic */
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+ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
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+ msleep(20);
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+ reg &= ~AR2315_RESET_PCIDMA;
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+ ar231x_write_reg(AR2315_RESET, reg);
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+ msleep(20);
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+
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+ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
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+ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
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+
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+ ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
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+ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
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+ ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
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+ ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
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+ AR2315_IF_PCI | AR2315_IF_PCI_HOST |
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+ AR2315_IF_PCI_INTR | (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
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+ AR2315_IF_PCI_CLK_SHIFT));
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+
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+ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
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+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
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+ AR2315_PCIRST_LOW);
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+ msleep(100);
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+
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+ /* Bring the PCI out of reset */
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+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
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+ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
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+
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+ ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
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+ 0x1E | /* 1GB uncached */
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+ (1 << 5) | /* Enable uncached */
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+ (0x2 << 30) /* Base: 0x80000000 */);
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+ ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
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+
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+ msleep(500);
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+
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+ res = ar2315_pci_host_setup();
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+ if (res)
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+ return res;
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+
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+ ar2315_pci_irq_init();
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+
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+ register_pci_controller(&ar2315_pci_controller);
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+
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+ return 0;
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+}
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+
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+static struct platform_driver ar2315_pci_driver = {
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+ .probe = ar2315_pci_probe,
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+ .driver = {
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+ .name = "ar2315-pci",
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+ .owner = THIS_MODULE,
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+ },
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+};
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+
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+static int __init ar2315_pci_init(void)
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+{
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+ return platform_driver_register(&ar2315_pci_driver);
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+}
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+arch_initcall(ar2315_pci_init);
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+
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+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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+{
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+ return AR2315_PCI_IRQ_EXT;
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+}
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+
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+int pcibios_plat_dev_init(struct pci_dev *dev)
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+{
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+ return 0;
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+}
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--- a/arch/mips/ar231x/Kconfig
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+++ b/arch/mips/ar231x/Kconfig
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@@ -9,3 +9,10 @@ config SOC_AR2315
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depends on ATHEROS_AR231X
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select GPIO_AR2315
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default y
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+
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+config PCI_AR2315
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+ bool "AR2315 PCI controller support"
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+ depends on SOC_AR2315
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+ select HW_HAS_PCI
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+ select PCI
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+ default y
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--- a/arch/mips/ar231x/ar2315.c
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+++ b/arch/mips/ar231x/ar2315.c
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@@ -77,6 +77,10 @@ ar2315_irq_dispatch(void)
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do_IRQ(AR2315_IRQ_WLAN0_INTRS);
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else if (pending & CAUSEF_IP4)
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do_IRQ(AR2315_IRQ_ENET0_INTRS);
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+#ifdef CONFIG_PCI_AR2315
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+ else if (pending & CAUSEF_IP5)
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+ do_IRQ(AR2315_IRQ_LCBUS_PCI);
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+#endif
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else if (pending & CAUSEF_IP2)
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do_IRQ(AR2315_IRQ_MISC_INTRS);
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else if (pending & CAUSEF_IP7)
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@@ -458,3 +462,18 @@ ar2315_plat_setup(void)
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ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
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ar2315_apb_frequency());
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}
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+
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+#ifdef CONFIG_PCI_AR2315
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+static int __init ar2315_pci_init(void)
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+{
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+ struct platform_device *pdev;
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+
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+ if (!is_2315() || ar231x_devtype != DEV_TYPE_AR2315)
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+ return -ENODEV;
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+
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+ pdev = platform_device_register_simple("ar2315-pci", -1, NULL, 0);
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+
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+ return pdev ? 0 : -ENODEV;
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+}
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+arch_initcall(ar2315_pci_init);
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+#endif
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