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From 3f450d3eea14799b14192231840c1753a660f150 Mon Sep 17 00:00:00 2001
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From: Abhishek Sahu <absahu@codeaurora.org>
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Date: Mon, 12 Mar 2018 18:44:56 +0530
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Subject: [PATCH 07/13] i2c: qup: proper error handling for i2c error in BAM
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mode
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Currently the i2c error handling in BAM mode is not working
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properly in stress condition.
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1. After an error, the FIFO are being written with FLUSH and
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EOT tags which should not be required since already these tags
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have been written in BAM descriptor itself.
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2. QUP state is being moved to RESET in IRQ handler in case
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of error. When QUP HW encounters an error in BAM mode then it
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moves the QUP STATE to PAUSE state. In this case, I2C_FLUSH
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command needs to be executed while moving to RUN_STATE by writing
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to the QUP_STATE register with the I2C_FLUSH bit set to 1.
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3. In Error case, sometimes, QUP generates more than one
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interrupt which will trigger the complete again. After an error,
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the flush operation will be scheduled after doing
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reinit_completion which should be triggered by BAM IRQ callback.
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If the second QUP IRQ comes during this time then it will call
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the complete and the transfer function will assume the all the
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BAM HW descriptors have been completed.
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4. The release DMA is being called after each error which
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will free the DMA tx and rx channels. The error like NACK is very
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common in I2C transfer and every time this will be overhead. Now,
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since the error handling is proper so this release channel can be
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completely avoided.
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Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
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Reviewed-by: Sricharan R <sricharan@codeaurora.org>
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Reviewed-by: Austin Christ <austinwc@codeaurora.org>
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Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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---
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drivers/i2c/busses/i2c-qup.c | 25 ++++++++++++++++---------
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1 file changed, 16 insertions(+), 9 deletions(-)
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--- a/drivers/i2c/busses/i2c-qup.c
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+++ b/drivers/i2c/busses/i2c-qup.c
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@@ -219,9 +219,24 @@ static irqreturn_t qup_i2c_interrupt(int
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if (bus_err)
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writel(bus_err, qup->base + QUP_I2C_STATUS);
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+ /*
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+ * Check for BAM mode and returns if already error has come for current
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+ * transfer. In Error case, sometimes, QUP generates more than one
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+ * interrupt.
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+ */
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+ if (qup->use_dma && (qup->qup_err || qup->bus_err))
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+ return IRQ_HANDLED;
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+
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/* Reset the QUP State in case of error */
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if (qup_err || bus_err) {
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- writel(QUP_RESET_STATE, qup->base + QUP_STATE);
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+ /*
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+ * Don’t reset the QUP state in case of BAM mode. The BAM
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+ * flush operation needs to be scheduled in transfer function
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+ * which will clear the remaining schedule descriptors in BAM
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+ * HW FIFO and generates the BAM interrupt.
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+ */
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+ if (!qup->use_dma)
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+ writel(QUP_RESET_STATE, qup->base + QUP_STATE);
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goto done;
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}
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@@ -847,20 +862,12 @@ static int qup_i2c_bam_do_xfer(struct qu
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goto desc_err;
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}
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- if (rx_cnt)
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- writel(QUP_BAM_INPUT_EOT,
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- qup->base + QUP_OUT_FIFO_BASE);
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-
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- writel(QUP_BAM_FLUSH_STOP, qup->base + QUP_OUT_FIFO_BASE);
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-
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qup_i2c_flush(qup);
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/* wait for remaining interrupts to occur */
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if (!wait_for_completion_timeout(&qup->xfer, HZ))
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dev_err(qup->dev, "flush timed out\n");
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- qup_i2c_rel_dma(qup);
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-
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ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
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}
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