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233 lines
6.0 KiB
Diff
233 lines
6.0 KiB
Diff
--- a/drivers/bcma/driver_chipcommon_nflash.c
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+++ b/drivers/bcma/driver_chipcommon_nflash.c
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@@ -2,16 +2,23 @@
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* Broadcom specific AMBA
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* ChipCommon NAND flash interface
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*
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+ * Copyright 2011, Tathagata Das <tathagata@alumnux.com>
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+ * Copyright 2010, Broadcom Corporation
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+ *
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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+#include <linux/delay.h>
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+#include <linux/mtd/bcm47xx_nand.h>
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+#include <linux/mtd/nand.h>
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#include <linux/platform_device.h>
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#include <linux/bcma/bcma.h>
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+#include <linux/bcma/bcma_driver_chipcommon.h>
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#include "bcma_private.h"
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struct platform_device bcma_nflash_dev = {
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- .name = "bcma_nflash",
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+ .name = "bcm47xx-nflash",
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.num_resources = 0,
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};
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@@ -31,6 +38,11 @@ int bcma_nflash_init(struct bcma_drv_cc
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return -ENODEV;
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}
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+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
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+ bcma_err(bus, "NAND flash support for BCM4706 not implemented\n");
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+ return -ENOTSUPP;
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+ }
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+
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cc->nflash.present = true;
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if (cc->core->id.rev == 38 &&
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(cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
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@@ -42,3 +54,141 @@ int bcma_nflash_init(struct bcma_drv_cc
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return 0;
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}
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+
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+/* Issue a nand flash command */
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+static inline void bcma_nflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
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+{
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+ bcma_cc_write32(cc, NAND_CMD_START, opcode);
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+ bcma_cc_read32(cc, NAND_CMD_START);
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+}
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+
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+/* Check offset and length */
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+static int bcma_nflash_offset_is_valid(struct bcma_drv_cc *cc, u32 offset, u32 len, u32 mask)
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+{
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+ if ((offset & mask) != 0 || (len & mask) != 0) {
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+ pr_err("%s(): Address is not aligned. offset: %x, len: %x, mask: %x\n", __func__, offset, len, mask);
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+ return 1;
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+ }
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+
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+ if ((((offset + len) >> 20) >= cc->nflash.size) &&
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+ (((offset + len) & ((1 << 20) - 1)) != 0)) {
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+ pr_err("%s(): Address is outside Flash memory region. offset: %x, len: %x, mask: %x\n", __func__, offset, len, mask);
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+ return 1;
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+ }
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+
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+ return 0;
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+}
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+
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+#define NF_RETRIES 1000000
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+
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+/* Poll for command completion. Returns zero when complete. */
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+int bcma_nflash_poll(struct bcma_drv_cc *cc)
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+{
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+ u32 retries = NF_RETRIES;
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+ u32 pollmask = NIST_CTRL_READY|NIST_FLASH_READY;
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+ u32 mask;
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+
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+ while (retries--) {
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+ mask = bcma_cc_read32(cc, NAND_INTFC_STATUS) & pollmask;
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+ if (mask == pollmask)
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+ return 0;
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+ cpu_relax();
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+ }
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+
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+ if (!retries) {
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+ pr_err("bcma_nflash_poll: not ready\n");
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+ return -1;
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+ }
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+
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+ return 0;
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+}
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+
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+/* Read len bytes starting at offset into buf. Returns number of bytes read. */
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+int bcma_nflash_read(struct bcma_drv_cc *cc, u32 offset, u32 len, u8 *buf)
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+{
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+ u32 mask;
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+ int i;
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+ u32 *to, val, res;
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+
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+ mask = NFL_SECTOR_SIZE - 1;
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+ if (bcma_nflash_offset_is_valid(cc, offset, len, mask))
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+ return 0;
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+
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+ to = (u32 *)buf;
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+ res = len;
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+ while (res > 0) {
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+ bcma_cc_write32(cc, NAND_CMD_ADDR, offset);
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+ bcma_nflash_cmd(cc, NCMD_PAGE_RD);
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+ if (bcma_nflash_poll(cc) < 0)
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+ break;
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+ val = bcma_cc_read32(cc, NAND_INTFC_STATUS);
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+ if ((val & NIST_CACHE_VALID) == 0)
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+ break;
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+ bcma_cc_write32(cc, NAND_CACHE_ADDR, 0);
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+ for (i = 0; i < NFL_SECTOR_SIZE; i += 4, to++) {
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+ *to = bcma_cc_read32(cc, NAND_CACHE_DATA);
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+ }
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+ res -= NFL_SECTOR_SIZE;
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+ offset += NFL_SECTOR_SIZE;
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+ }
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+ return (len - res);
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+}
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+
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+/* Write len bytes starting at offset into buf. Returns success (0) or failure (!0).
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+ * Should poll for completion.
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+ */
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+int bcma_nflash_write(struct bcma_drv_cc *cc, u32 offset, u32 len,
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+ const u8 *buf)
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+{
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+ u32 mask;
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+ int i;
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+ u32 *from, res, reg;
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+
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+ mask = cc->nflash.pagesize - 1;
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+ if (bcma_nflash_offset_is_valid(cc, offset, len, mask))
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+ return 1;
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+
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+ /* disable partial page enable */
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+ reg = bcma_cc_read32(cc, NAND_ACC_CONTROL);
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+ reg &= ~NAC_PARTIAL_PAGE_EN;
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+ bcma_cc_write32(cc, NAND_ACC_CONTROL, reg);
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+
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+ from = (u32 *)buf;
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+ res = len;
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+ while (res > 0) {
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+ bcma_cc_write32(cc, NAND_CACHE_ADDR, 0);
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+ for (i = 0; i < cc->nflash.pagesize; i += 4, from++) {
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+ if (i % 512 == 0)
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+ bcma_cc_write32(cc, NAND_CMD_ADDR, i);
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+ bcma_cc_write32(cc, NAND_CACHE_DATA, *from);
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+ }
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+ bcma_cc_write32(cc, NAND_CMD_ADDR, offset + cc->nflash.pagesize - 512);
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+ bcma_nflash_cmd(cc, NCMD_PAGE_PROG);
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+ if (bcma_nflash_poll(cc) < 0)
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+ break;
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+ res -= cc->nflash.pagesize;
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+ offset += cc->nflash.pagesize;
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+ }
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+
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+ if (res <= 0)
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+ return 0;
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+ else
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+ return (len - res);
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+}
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+
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+/* Erase a region. Returns success (0) or failure (-1).
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+ * Poll for completion.
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+ */
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+int bcma_nflash_erase(struct bcma_drv_cc *cc, u32 offset)
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+{
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+ if ((offset >> 20) >= cc->nflash.size)
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+ return -1;
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+ if ((offset & (cc->nflash.blocksize - 1)) != 0)
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+ return -1;
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+
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+ bcma_cc_write32(cc, NAND_CMD_ADDR, offset);
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+ bcma_nflash_cmd(cc, NCMD_BLOCK_ERASE);
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+ if (bcma_nflash_poll(cc) < 0)
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+ return -1;
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+ return 0;
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+}
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--- a/include/linux/bcma/bcma_driver_chipcommon.h
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+++ b/include/linux/bcma/bcma_driver_chipcommon.h
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@@ -5,6 +5,7 @@
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#include <linux/gpio.h>
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#include <linux/mtd/bcm47xx_sflash.h>
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+#include <linux/mtd/bcm47xx_nand.h>
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/** ChipCommon core registers. **/
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#define BCMA_CC_ID 0x0000
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@@ -522,17 +523,6 @@ struct bcma_pflash {
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};
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-#ifdef CONFIG_BCMA_NFLASH
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-struct mtd_info;
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-
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-struct bcma_nflash {
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- bool present;
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- bool boot; /* This is the flash the SoC boots from */
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-
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- struct mtd_info *mtd;
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-};
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-#endif
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-
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struct bcma_serial_port {
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void *regs;
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unsigned long clockspeed;
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@@ -558,7 +548,7 @@ struct bcma_drv_cc {
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struct bcm47xx_sflash sflash;
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#endif
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#ifdef CONFIG_BCMA_NFLASH
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- struct bcma_nflash nflash;
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+ struct bcm47xx_nflash nflash;
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#endif
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int nr_serial_ports;
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@@ -625,4 +615,13 @@ extern void bcma_chipco_regctl_maskset(s
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u32 offset, u32 mask, u32 set);
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extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
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+#ifdef CONFIG_BCMA_NFLASH
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+/* Chipcommon nflash support. */
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+int bcma_nflash_read(struct bcma_drv_cc *cc, u32 offset, u32 len, u8 *buf);
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+int bcma_nflash_poll(struct bcma_drv_cc *cc);
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+int bcma_nflash_write(struct bcma_drv_cc *cc, u32 offset, u32 len, const u8 *buf);
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+int bcma_nflash_erase(struct bcma_drv_cc *cc, u32 offset);
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+int bcma_nflash_commit(struct bcma_drv_cc *cc, u32 offset, u32 len, const u8 *buf);
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+#endif
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+
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#endif /* LINUX_BCMA_DRIVER_CC_H_ */
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