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239 lines
8.5 KiB
Diff
239 lines
8.5 KiB
Diff
From: Felix Fietkau <nbd@nbd.name>
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Date: Tue, 6 Mar 2018 13:23:20 +0100
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Subject: [PATCH] MIPS: ath79: pass PLL base to clock init functions
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Preparation for passing the mapped base via DT
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -79,7 +79,7 @@ static struct clk * __init ath79_set_ff_
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return clk;
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}
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-static void __init ar71xx_clocks_init(void)
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+static void __init ar71xx_clocks_init(void __iomem *pll_base)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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@@ -91,7 +91,7 @@ static void __init ar71xx_clocks_init(vo
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ref_rate = AR71XX_BASE_FREQ;
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- pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
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+ pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
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div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
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freq = div * ref_rate;
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@@ -129,13 +129,13 @@ static void __init ar724x_clk_init(struc
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ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
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}
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-static void __init ar724x_clocks_init(void)
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+static void __init ar724x_clocks_init(void __iomem *pll_base)
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{
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struct clk *ref_clk;
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ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
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- ar724x_clk_init(ref_clk, ath79_pll_base);
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+ ar724x_clk_init(ref_clk, pll_base);
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}
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static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
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@@ -196,7 +196,7 @@ static void __init ar9330_clk_init(struc
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ref_div * out_div * ahb_div);
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}
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-static void __init ar933x_clocks_init(void)
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+static void __init ar933x_clocks_init(void __iomem *pll_base)
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{
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struct clk *ref_clk;
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unsigned long ref_rate;
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@@ -233,7 +233,7 @@ static u32 __init ar934x_get_pll_freq(u3
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return ret;
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}
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-static void __init ar934x_clocks_init(void)
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+static void __init ar934x_clocks_init(void __iomem *pll_base)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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@@ -264,7 +264,7 @@ static void __init ar934x_clocks_init(vo
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AR934X_SRIF_DPLL1_REFDIV_MASK;
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frac = 1 << 18;
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} else {
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- pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
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+ pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
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out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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@@ -291,7 +291,7 @@ static void __init ar934x_clocks_init(vo
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AR934X_SRIF_DPLL1_REFDIV_MASK;
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frac = 1 << 18;
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} else {
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- pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
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+ pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
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out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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@@ -306,7 +306,7 @@ static void __init ar934x_clocks_init(vo
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ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
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nfrac, frac, out_div);
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- clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
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+ clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
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postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
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@@ -346,7 +346,7 @@ static void __init ar934x_clocks_init(vo
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iounmap(dpll_base);
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}
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-static void __init qca953x_clocks_init(void)
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+static void __init qca953x_clocks_init(void __iomem *pll_base)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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@@ -362,7 +362,7 @@ static void __init qca953x_clocks_init(v
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else
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ref_rate = 25 * 1000 * 1000;
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- pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
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+ pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
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out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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@@ -376,7 +376,7 @@ static void __init qca953x_clocks_init(v
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cpu_pll += frac * (ref_rate >> 6) / ref_div;
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cpu_pll /= (1 << out_div);
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- pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
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+ pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
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out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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@@ -390,7 +390,7 @@ static void __init qca953x_clocks_init(v
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ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
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ddr_pll /= (1 << out_div);
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- clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
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+ clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
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postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
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@@ -428,7 +428,7 @@ static void __init qca953x_clocks_init(v
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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}
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-static void __init qca955x_clocks_init(void)
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+static void __init qca955x_clocks_init(void __iomem *pll_base)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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@@ -444,7 +444,7 @@ static void __init qca955x_clocks_init(v
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else
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ref_rate = 25 * 1000 * 1000;
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- pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
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+ pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
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out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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@@ -458,7 +458,7 @@ static void __init qca955x_clocks_init(v
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cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
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cpu_pll /= (1 << out_div);
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- pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
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+ pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
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out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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@@ -472,7 +472,7 @@ static void __init qca955x_clocks_init(v
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ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
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ddr_pll /= (1 << out_div);
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- clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
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+ clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
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postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
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@@ -510,7 +510,7 @@ static void __init qca955x_clocks_init(v
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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}
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-static void __init qca956x_clocks_init(void)
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+static void __init qca956x_clocks_init(void __iomem *pll_base)
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{
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unsigned long ref_rate;
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unsigned long cpu_rate;
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@@ -526,13 +526,13 @@ static void __init qca956x_clocks_init(v
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else
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ref_rate = 25 * 1000 * 1000;
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- pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
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+ pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
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out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
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- pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
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+ pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
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nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
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QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
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hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
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@@ -545,12 +545,12 @@ static void __init qca956x_clocks_init(v
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cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
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cpu_pll /= (1 << out_div);
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- pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
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+ pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
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out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
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ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
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- pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
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+ pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
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nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
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QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
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hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
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@@ -563,7 +563,7 @@ static void __init qca956x_clocks_init(v
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ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
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ddr_pll /= (1 << out_div);
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- clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
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+ clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);
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postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
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@@ -607,19 +607,19 @@ void __init ath79_clocks_init(void)
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const char *uart;
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if (soc_is_ar71xx())
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- ar71xx_clocks_init();
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+ ar71xx_clocks_init(ath79_pll_base);
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else if (soc_is_ar724x() || soc_is_ar913x())
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- ar724x_clocks_init();
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+ ar724x_clocks_init(ath79_pll_base);
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else if (soc_is_ar933x())
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- ar933x_clocks_init();
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+ ar933x_clocks_init(ath79_pll_base);
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else if (soc_is_ar934x())
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- ar934x_clocks_init();
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+ ar934x_clocks_init(ath79_pll_base);
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else if (soc_is_qca953x())
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- qca953x_clocks_init();
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+ qca953x_clocks_init(ath79_pll_base);
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else if (soc_is_qca955x())
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- qca955x_clocks_init();
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+ qca955x_clocks_init(ath79_pll_base);
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else if (soc_is_qca956x() || soc_is_tp9343())
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- qca956x_clocks_init();
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+ qca956x_clocks_init(ath79_pll_base);
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else
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BUG();
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