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113 lines
3.6 KiB
Diff
113 lines
3.6 KiB
Diff
From 23cd071c47c064d56921975d196dc22177069dea Mon Sep 17 00:00:00 2001
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From: Yunhui Cui <yunhui.cui@nxp.com>
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Date: Wed, 24 Feb 2016 15:14:01 +0800
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Subject: [PATCH 104/113] mtd: fsl-quadspi: Add quad mode for flash n25q128
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Add some lut_tables to support quad mode for flash n25q128
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on the board ls1021a-twr and solve flash Spansion and Micron
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command conflict.
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In switch {}, The value of command SPINOR_OP_RD_EVCR and
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SPINOR_OP_SPANSION_RDAR is the same. They have to share
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the same seq_id: SEQID_RDAR_OR_RD_EVCR.
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Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
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---
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drivers/mtd/spi-nor/fsl-quadspi.c | 47 ++++++++++++++++++++++++++++---------
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1 file changed, 36 insertions(+), 11 deletions(-)
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--- a/drivers/mtd/spi-nor/fsl-quadspi.c
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+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
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@@ -207,9 +207,9 @@
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#define SEQID_RDCR 9
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#define SEQID_EN4B 10
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#define SEQID_BRWR 11
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-#define SEQID_RDAR 12
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+#define SEQID_RDAR_OR_RD_EVCR 12
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#define SEQID_WRAR 13
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-
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+#define SEQID_WD_EVCR 14
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#define QUADSPI_MIN_IOMAP SZ_4M
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@@ -393,6 +393,7 @@ static void fsl_qspi_init_lut(struct fsl
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int rxfifo = q->devtype_data->rxfifo;
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u32 lut_base;
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int i;
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+ const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data;
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struct spi_nor *nor = &q->nor[0];
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u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
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@@ -489,16 +490,26 @@ static void fsl_qspi_init_lut(struct fsl
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qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
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base + QUADSPI_LUT(lut_base));
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+
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/*
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- * Read any device register.
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- * Used for Spansion S25FS-S family flash only.
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+ * Flash Micron and Spansion command confilict
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+ * use the same value 0x65. But it indicates different meaning.
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*/
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- lut_base = SEQID_RDAR * 4;
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- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
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- LUT1(ADDR, PAD1, ADDR24BIT),
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- base + QUADSPI_LUT(lut_base));
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- qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
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- base + QUADSPI_LUT(lut_base + 1));
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+ lut_base = SEQID_RDAR_OR_RD_EVCR * 4;
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+ if (devtype_data->devtype == FSL_QUADSPI_LS2080A) {
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+ /*
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+ * Read any device register.
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+ * Used for Spansion S25FS-S family flash only.
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+ */
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+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
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+ LUT1(ADDR, PAD1, ADDR24BIT),
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+ base + QUADSPI_LUT(lut_base));
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+ qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
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+ base + QUADSPI_LUT(lut_base + 1));
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+ } else {
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+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RD_EVCR),
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+ base + QUADSPI_LUT(lut_base));
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+ }
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/*
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* Write any device register.
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@@ -511,6 +522,11 @@ static void fsl_qspi_init_lut(struct fsl
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qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1),
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base + QUADSPI_LUT(lut_base + 1));
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+ /* Write EVCR register */
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+ lut_base = SEQID_WD_EVCR * 4;
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+ qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WD_EVCR),
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+ base + QUADSPI_LUT(lut_base));
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+
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fsl_qspi_lock_lut(q);
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}
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@@ -523,8 +539,15 @@ static int fsl_qspi_get_seqid(struct fsl
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case SPINOR_OP_READ_FAST:
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case SPINOR_OP_READ4_FAST:
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return SEQID_READ;
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+ /*
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+ * Spansion & Micron use the same command value 0x65
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+ * Spansion: SPINOR_OP_SPANSION_RDAR, read any register.
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+ * Micron: SPINOR_OP_RD_EVCR,
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+ * read enhanced volatile configuration register.
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+ * case SPINOR_OP_RD_EVCR:
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+ */
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case SPINOR_OP_SPANSION_RDAR:
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- return SEQID_RDAR;
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+ return SEQID_RDAR_OR_RD_EVCR;
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case SPINOR_OP_SPANSION_WRAR:
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return SEQID_WRAR;
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case SPINOR_OP_WREN:
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@@ -550,6 +573,8 @@ static int fsl_qspi_get_seqid(struct fsl
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return SEQID_EN4B;
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case SPINOR_OP_BRWR:
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return SEQID_BRWR;
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+ case SPINOR_OP_WD_EVCR:
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+ return SEQID_WD_EVCR;
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default:
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if (cmd == q->nor[0].erase_opcode)
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return SEQID_SE;
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