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1080 lines
27 KiB
Diff
1080 lines
27 KiB
Diff
From 51d5ca9e151eb323bd965e72ad1e1dc93fcf7b13 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 5 Jan 2016 12:16:17 +0100
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Subject: [PATCH 023/102] ARM: dts: mediatek: add MT7623 basic support
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This adds basic chip support for Mediatek MT7623.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/arm/boot/dts/Makefile | 1 +
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arch/arm/boot/dts/mt7623-evb.dts | 421 ++++++++++++++++++++++++++
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arch/arm/boot/dts/mt7623.dtsi | 601 +++++++++++++++++++++++++++++++++++++
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arch/arm/mach-mediatek/Kconfig | 4 +
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arch/arm/mach-mediatek/mediatek.c | 1 +
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5 files changed, 1028 insertions(+)
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create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
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create mode 100644 arch/arm/boot/dts/mt7623.dtsi
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -774,6 +774,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt6580-evbp1.dtb \
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mt6589-aquaris5.dtb \
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mt6592-evb.dtb \
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+ mt7623-evb.dtb \
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mt8127-moose.dtb \
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mt8135-evbp1.dtb
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dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
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--- /dev/null
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+++ b/arch/arm/boot/dts/mt7623-evb.dts
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@@ -0,0 +1,421 @@
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+/*
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+ * Copyright (c) 2016 MediaTek Inc.
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+ * Author: John Crispin <blogic@openwrt.org>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+/dts-v1/;
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+
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+#include "mt7623.dtsi"
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ model = "MediaTek MT7623 evaluation board";
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+ compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
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+
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+ chosen {
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+ stdout-path = &uart2;
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+ };
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+
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+ memory {
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+ reg = <0 0x80000000 0 0x20000000>;
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+ };
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+
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+ usb_p1_vbus: regulator@0 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "usb_vbus";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
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+ enable-active-high;
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+ };
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+};
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+
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+&cpu0 {
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+ proc-supply = <&mt6323_vproc_reg>;
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+};
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+
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+&cpu1 {
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+ proc-supply = <&mt6323_vproc_reg>;
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+};
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+
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+&cpu2 {
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+ proc-supply = <&mt6323_vproc_reg>;
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+};
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+
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+&cpu3 {
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+ proc-supply = <&mt6323_vproc_reg>;
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+};
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+
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+&pwrap {
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+ pmic: mt6323 {
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+ compatible = "mediatek,mt6323";
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+ interrupt-parent = <&pio>;
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+ interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+
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+ mt6323regulator: mt6323regulator{
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+ compatible = "mediatek,mt6323-regulator";
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+
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+ mt6323_vproc_reg: buck_vproc{
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+ regulator-name = "vproc";
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+ regulator-min-microvolt = < 700000>;
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+ regulator-max-microvolt = <1350000>;
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+ regulator-ramp-delay = <12500>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ mt6323_vsys_reg: buck_vsys{
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+ regulator-name = "vsys";
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+ regulator-min-microvolt = <1400000>;
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+ regulator-max-microvolt = <2987500>;
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+ regulator-ramp-delay = <25000>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ mt6323_vpa_reg: buck_vpa{
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+ regulator-name = "vpa";
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+ regulator-min-microvolt = < 500000>;
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+ regulator-max-microvolt = <3650000>;
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+ };
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+
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+ mt6323_vtcxo_reg: ldo_vtcxo{
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+ regulator-name = "vtcxo";
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+ regulator-min-microvolt = <2800000>;
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+ regulator-max-microvolt = <2800000>;
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+ regulator-enable-ramp-delay = <90>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ mt6323_vcn28_reg: ldo_vcn28{
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+ regulator-name = "vcn28";
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+ regulator-min-microvolt = <2800000>;
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+ regulator-max-microvolt = <2800000>;
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+ regulator-enable-ramp-delay = <185>;
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+ };
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+
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+ mt6323_vcn33_bt_reg: ldo_vcn33_bt{
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+ regulator-name = "vcn33_bt";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3600000>;
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+ regulator-enable-ramp-delay = <185>;
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+ };
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+
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+ mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
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+ regulator-name = "vcn33_wifi";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3600000>;
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+ regulator-enable-ramp-delay = <185>;
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+ };
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+
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+ mt6323_va_reg: ldo_va{
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+ regulator-name = "va";
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+ regulator-min-microvolt = <2800000>;
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+ regulator-max-microvolt = <2800000>;
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+ regulator-enable-ramp-delay = <216>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ mt6323_vcama_reg: ldo_vcama{
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+ regulator-name = "vcama";
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+ regulator-min-microvolt = <1500000>;
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+ regulator-max-microvolt = <2800000>;
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+ regulator-enable-ramp-delay = <216>;
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+ };
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+
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+ mt6323_vio28_reg: ldo_vio28{
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+ regulator-name = "vio28";
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+ regulator-min-microvolt = <2800000>;
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+ regulator-max-microvolt = <2800000>;
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+ regulator-enable-ramp-delay = <216>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ mt6323_vusb_reg: ldo_vusb{
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+ regulator-name = "vusb";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-enable-ramp-delay = <216>;
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+ regulator-boot-on;
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+ };
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+
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+ mt6323_vmc_reg: ldo_vmc{
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+ regulator-name = "vmc";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-enable-ramp-delay = <36>;
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+ regulator-boot-on;
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+ };
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+
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+ mt6323_vmch_reg: ldo_vmch{
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+ regulator-name = "vmch";
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+ regulator-min-microvolt = <3000000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-enable-ramp-delay = <36>;
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+ regulator-boot-on;
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+ };
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+
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+ mt6323_vemc3v3_reg: ldo_vemc3v3{
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+ regulator-name = "vemc3v3";
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+ regulator-min-microvolt = <3000000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-enable-ramp-delay = <36>;
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+ regulator-boot-on;
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+ };
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+
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+ mt6323_vgp1_reg: ldo_vgp1{
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+ regulator-name = "vgp1";
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+ regulator-min-microvolt = <1200000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-enable-ramp-delay = <216>;
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+ };
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+
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+ mt6323_vgp2_reg: ldo_vgp2{
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+ regulator-name = "vgp2";
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+ regulator-min-microvolt = <1200000>;
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+ regulator-max-microvolt = <3000000>;
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+ regulator-enable-ramp-delay = <216>;
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+ };
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+
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+ mt6323_vgp3_reg: ldo_vgp3{
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+ regulator-name = "vgp3";
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+ regulator-min-microvolt = <1200000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-enable-ramp-delay = <216>;
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+ };
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+
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+ mt6323_vcn18_reg: ldo_vcn18{
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+ regulator-name = "vcn18";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-enable-ramp-delay = <216>;
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+ };
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+
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+ mt6323_vsim1_reg: ldo_vsim1{
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+ regulator-name = "vsim1";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <3000000>;
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+ regulator-enable-ramp-delay = <216>;
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+ };
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+
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+ mt6323_vsim2_reg: ldo_vsim2{
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+ regulator-name = "vsim2";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <3000000>;
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+ regulator-enable-ramp-delay = <216>;
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+ };
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+
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+ mt6323_vrtc_reg: ldo_vrtc{
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+ regulator-name = "vrtc";
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+ regulator-min-microvolt = <2800000>;
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+ regulator-max-microvolt = <2800000>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ mt6323_vcamaf_reg: ldo_vcamaf{
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+ regulator-name = "vcamaf";
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+ regulator-min-microvolt = <1200000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-enable-ramp-delay = <216>;
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+ };
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+
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+ mt6323_vibr_reg: ldo_vibr{
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+ regulator-name = "vibr";
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+ regulator-min-microvolt = <1200000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-enable-ramp-delay = <36>;
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+ };
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+
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+ mt6323_vrf18_reg: ldo_vrf18{
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+ regulator-name = "vrf18";
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+ regulator-min-microvolt = <1825000>;
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+ regulator-max-microvolt = <1825000>;
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+ regulator-enable-ramp-delay = <187>;
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+ };
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+
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+ mt6323_vm_reg: ldo_vm{
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+ regulator-name = "vm";
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+ regulator-min-microvolt = <1200000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-enable-ramp-delay = <216>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ mt6323_vio18_reg: ldo_vio18{
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+ regulator-name = "vio18";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-enable-ramp-delay = <216>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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+ mt6323_vcamd_reg: ldo_vcamd{
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+ regulator-name = "vcamd";
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+ regulator-min-microvolt = <1200000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-enable-ramp-delay = <216>;
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+ };
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+
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+ mt6323_vcamio_reg: ldo_vcamio{
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+ regulator-name = "vcamio";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-enable-ramp-delay = <216>;
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+ };
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+ };
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+ };
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+};
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+
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+&uart2 {
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+ status = "okay";
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+};
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+
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+&pio {
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+ nand_pins_default: nanddefault {
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+ pins_dat {
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+ pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
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+ <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
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+ <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
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+ <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
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+ <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
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+ <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
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+ <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
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+ <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
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+ <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
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+ input-enable;
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+ drive-strength = <MTK_DRIVE_8mA>;
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+ bias-pull-up;
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+ };
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+
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+ pins_we {
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+ pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
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+ drive-strength = <MTK_DRIVE_8mA>;
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+ bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
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+ };
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+
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+ pins_ale {
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+ pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
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+ drive-strength = <MTK_DRIVE_8mA>;
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+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
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+ };
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+ };
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+
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+ eth_default: eth {
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+ pins_eth {
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+ pinmux = <MT7623_PIN_275_G2_MDC_FUNC_MDC>,
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+ <MT7623_PIN_276_G2_MDIO_FUNC_MDIO>,
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+ <MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN>,
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+ <MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3>,
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+ <MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2>,
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+ <MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1>,
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+ <MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0>,
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+ <MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC>,
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+ <MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC>,
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+ <MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0>,
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+ <MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1>,
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+ <MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2>,
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+ <MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3>,
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+ <MT7623_PIN_273_ESW_INT_FUNC_ESW_INT>,
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+ <MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
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+ };
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+
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+ pins_eth_rst {
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+ pinmux = <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
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+ output-low;
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+ };
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+ };
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+};
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+
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+&nandc {
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+ status = "okay";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&nand_pins_default>;
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+ nand@0 {
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+ reg = <0>;
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@C0000 {
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+ label = "uboot-env";
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+ reg = <0xC0000 0x40000>;
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+ };
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+
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+ partition@100000 {
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+ label = "factory";
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+ reg = <0x100000 0x40000>;
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+ };
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+
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+ partition@140000 {
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+ label = "kernel";
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+ reg = <0x140000 0x2000000>;
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+ };
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+
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+ partition@2140000 {
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+ label = "recovery";
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+ reg = <0x2140000 0x2000000>;
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+ };
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+
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+ partition@4140000 {
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+ label = "rootfs";
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+ reg = <0x4140000 0x1000000>;
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+ };
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+ };
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+ };
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+};
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+&bch {
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+ status = "okay";
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+};
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+
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+&usb1 {
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+ vusb33-supply = <&mt6323_vusb_reg>;
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+ vbus-supply = <&usb_p1_vbus>;
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+ status = "okay";
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+};
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+
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+&u3phy1 {
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+ status = "okay";
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+};
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+
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+&pcie {
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+ status = "okay";
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+};
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+
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+ð {
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+ status = "okay";
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+};
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+
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+&gmac1 {
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+ mac-address = [00 11 22 33 44 56];
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+ status = "okay";
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+};
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+
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+&gmac2 {
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+ mac-address = [00 11 22 33 44 55];
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+ status = "okay";
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+};
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+
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+&gsw {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <ð_default>;
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+ mediatek,reset-pin = <&pio 15 0>;
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+ status = "okay";
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+};
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--- /dev/null
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+++ b/arch/arm/boot/dts/mt7623.dtsi
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|
@@ -0,0 +1,601 @@
|
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+/*
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|
+ * Copyright (c) 2016 MediaTek Inc.
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|
+ * Author: John Crispin <blogic@openwrt.org>
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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|
+ *
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+ * This program is distributed in the hope that it will be useful,
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|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <dt-bindings/interrupt-controller/irq.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/clock/mt2701-clk.h>
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+#include <dt-bindings/power/mt2701-power.h>
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+#include <dt-bindings/phy/phy.h>
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+#include <dt-bindings/reset-controller/mt2701-resets.h>
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+#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
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+#include "skeleton64.dtsi"
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+
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+
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+/ {
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+ compatible = "mediatek,mt7623";
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+ interrupt-parent = <&sysirq>;
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ enable-method = "mediatek,mt6589-smp";
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+
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+ cpu0: cpu@0 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a7";
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+ reg = <0x0>;
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+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
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+ <&apmixedsys CLK_APMIXED_MAINPLL>;
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+ clock-names = "cpu", "intermediate";
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+ operating-points = <
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+ 598000 1150000
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+ 747500 1150000
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+ 1040000 1150000
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+ 1196000 1200000
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+ 1300000 1300000
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|
+ >;
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+ };
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+ cpu1: cpu@1 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a7";
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+ reg = <0x1>;
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+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
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+ <&apmixedsys CLK_APMIXED_MAINPLL>;
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+ clock-names = "cpu", "intermediate";
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+ operating-points = <
|
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+ 598000 1150000
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+ 747500 1150000
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+ 1040000 1150000
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+ 1196000 1200000
|
|
+ 1300000 1300000
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+ >;
|
|
+ };
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+ cpu2: cpu@2 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a7";
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+ reg = <0x2>;
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+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
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+ <&apmixedsys CLK_APMIXED_MAINPLL>;
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+ clock-names = "cpu", "intermediate";
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+ operating-points = <
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+ 598000 1150000
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+ 747500 1150000
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+ 1040000 1150000
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+ 1196000 1200000
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+ 1300000 1300000
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+ >;
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+ };
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+ cpu3: cpu@3 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a7";
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+ reg = <0x3>;
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+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
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+ <&apmixedsys CLK_APMIXED_MAINPLL>;
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+ clock-names = "cpu", "intermediate";
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+ operating-points = <
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+ 598000 1150000
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+ 747500 1150000
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+ 1040000 1150000
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+ 1196000 1200000
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+ 1300000 1300000
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+ >;
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+ };
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+ };
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+
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+ system_clk: dummy13m {
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+ compatible = "fixed-clock";
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+ clock-frequency = <13000000>;
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+ #clock-cells = <0>;
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+ };
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+
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+ rtc_clk: dummy32k {
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+ compatible = "fixed-clock";
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+ clock-frequency = <32000>;
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+ #clock-cells = <0>;
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+ clock-output-names = "clk32k";
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+ };
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+
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+ clk26m: dummy26m {
|
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+ compatible = "fixed-clock";
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+ clock-frequency = <26000000>;
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+ #clock-cells = <0>;
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+ clock-output-names = "clk26m";
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+ };
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+
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+ timer {
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+ compatible = "arm,armv7-timer";
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+ interrupt-parent = <&gic>;
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+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
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+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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+ clock-frequency = <13000000>;
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+ arm,cpu-registers-not-fw-configured;
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|
+ };
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+
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+ topckgen: power-controller@10000000 {
|
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+ compatible = "mediatek,mt7623-topckgen",
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+ "mediatek,mt2701-topckgen",
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+ "syscon";
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+ reg = <0 0x10000000 0 0x1000>;
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+ #clock-cells = <1>;
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+ };
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+
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+ infracfg: power-controller@10001000 {
|
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+ compatible = "mediatek,mt7623-infracfg",
|
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+ "mediatek,mt2701-infracfg",
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+ "syscon";
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+ reg = <0 0x10001000 0 0x1000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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+ pericfg: pericfg@10003000 {
|
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+ compatible = "mediatek,mt7623-pericfg",
|
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+ "mediatek,mt2701-pericfg",
|
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+ "syscon";
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+ reg = <0 0x10003000 0 0x1000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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+ pio: pinctrl@10005000 {
|
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+ compatible = "mediatek,mt7623-pinctrl";
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+ reg = <0 0x1000b000 0 0x1000>;
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+ mediatek,pctl-regmap = <&syscfg_pctl_a>;
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+ pins-are-numbered;
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ interrupt-controller;
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+ interrupt-parent = <&gic>;
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+ #interrupt-cells = <2>;
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+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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|
+ };
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+
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+ syscfg_pctl_a: syscfg@10005000 {
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+ compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
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+ reg = <0 0x10005000 0 0x1000>;
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|
+ };
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+
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+ scpsys: scpsys@10006000 {
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+ #power-domain-cells = <1>;
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+ compatible = "mediatek,mt7623-scpsys",
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+ "mediatek,mt2701-scpsys";
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+ reg = <0 0x10006000 0 0x1000>;
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+ infracfg = <&infracfg>;
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+ clocks = <&clk26m>,
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+ <&topckgen CLK_TOP_MM_SEL>;
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+ clock-names = "mfg", "mm";
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|
+ };
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+
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+ watchdog: watchdog@10007000 {
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+ compatible = "mediatek,mt7623-wdt",
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+ "mediatek,mt6589-wdt";
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+ reg = <0 0x10007000 0 0x100>;
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+ };
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+
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+ timer: timer@10008000 {
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+ compatible = "mediatek,mt7623-timer",
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+ "mediatek,mt6577-timer";
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+ reg = <0 0x10008000 0 0x80>;
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+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&system_clk>, <&rtc_clk>;
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+ clock-names = "system-clk", "rtc-clk";
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|
+ };
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+
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+ pwrap: pwrap@1000d000 {
|
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+ compatible = "mediatek,mt7623-pwrap",
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+ "mediatek,mt2701-pwrap";
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+ reg = <0 0x1000d000 0 0x1000>;
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+ reg-names = "pwrap";
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+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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+ resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
|
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+ reset-names = "pwrap";
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|
+ clocks = <&infracfg CLK_INFRA_PMICSPI>,
|
|
+ <&infracfg CLK_INFRA_PMICWRAP>;
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|
+ clock-names = "spi", "wrap";
|
|
+ };
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|
+
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+ sysirq: interrupt-controller@10200100 {
|
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+ compatible = "mediatek,mt7623-sysirq",
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+ "mediatek,mt6577-sysirq";
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ interrupt-parent = <&gic>;
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+ reg = <0 0x10200100 0 0x1c>;
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+ };
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+
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+ apmixedsys: apmixedsys@10209000 {
|
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+ compatible = "mediatek,mt7623-apmixedsys",
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+ "mediatek,mt2701-apmixedsys";
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+ reg = <0 0x10209000 0 0x1000>;
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+ #clock-cells = <1>;
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+ };
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+
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+ gic: interrupt-controller@10211000 {
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+ compatible = "arm,cortex-a7-gic";
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ interrupt-parent = <&gic>;
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+ reg = <0 0x10211000 0 0x1000>,
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+ <0 0x10212000 0 0x1000>,
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+ <0 0x10214000 0 0x2000>,
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+ <0 0x10216000 0 0x2000>;
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|
+ };
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+
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+ i2c0: i2c@11007000 {
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+ compatible = "mediatek,mt7623-i2c",
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+ "mediatek,mt6577-i2c";
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+ reg = <0 0x11007000 0 0x70>,
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+ <0 0x11000200 0 0x80>;
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+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
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+ clock-div = <16>;
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+ clocks = <&pericfg CLK_PERI_I2C0>,
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+ <&pericfg CLK_PERI_AP_DMA>;
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+ clock-names = "main", "dma";
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+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
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|
+ status = "disabled";
|
|
+ };
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+
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+ i2c1: i2c@11008000 {
|
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+ compatible = "mediatek,mt7623-i2c",
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+ "mediatek,mt6577-i2c";
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+ reg = <0 0x11008000 0 0x70>,
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+ <0 0x11000280 0 0x80>;
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+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
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+ clock-div = <16>;
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+ clocks = <&pericfg CLK_PERI_I2C1>,
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+ <&pericfg CLK_PERI_AP_DMA>;
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+ clock-names = "main", "dma";
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+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
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+
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+ i2c2: i2c@11009000 {
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+ compatible = "mediatek,mt7623-i2c",
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+ "mediatek,mt6577-i2c";
|
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+ reg = <0 0x11009000 0 0x70>,
|
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+ <0 0x11000300 0 0x80>;
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+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
|
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+ clock-div = <16>;
|
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+ clocks = <&pericfg CLK_PERI_I2C2>,
|
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+ <&pericfg CLK_PERI_AP_DMA>;
|
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+ clock-names = "main", "dma";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
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+ uart0: serial@11002000 {
|
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+ compatible = "mediatek,mt7623-uart",
|
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+ "mediatek,mt6577-uart";
|
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+ reg = <0 0x11002000 0 0x400>;
|
|
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
|
|
+ clocks = <&pericfg CLK_PERI_UART0_SEL>,
|
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+ <&pericfg CLK_PERI_UART0>;
|
|
+ clock-names = "baud", "bus";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart1: serial@11003000 {
|
|
+ compatible = "mediatek,mt7623-uart",
|
|
+ "mediatek,mt6577-uart";
|
|
+ reg = <0 0x11003000 0 0x400>;
|
|
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
|
|
+ clocks = <&pericfg CLK_PERI_UART1_SEL>,
|
|
+ <&pericfg CLK_PERI_UART1>;
|
|
+ clock-names = "baud", "bus";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart2: serial@11004000 {
|
|
+ compatible = "mediatek,mt7623-uart",
|
|
+ "mediatek,mt6577-uart";
|
|
+ reg = <0 0x11004000 0 0x400>;
|
|
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
|
|
+ clocks = <&pericfg CLK_PERI_UART2_SEL>,
|
|
+ <&pericfg CLK_PERI_UART2>;
|
|
+ clock-names = "baud", "bus";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ uart3: serial@11005000 {
|
|
+ compatible = "mediatek,mt7623-uart",
|
|
+ "mediatek,mt6577-uart";
|
|
+ reg = <0 0x11005000 0 0x400>;
|
|
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
|
|
+ clocks = <&pericfg CLK_PERI_UART3_SEL>,
|
|
+ <&pericfg CLK_PERI_UART3>;
|
|
+ clock-names = "baud", "bus";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ spi: spi@1100a000 {
|
|
+ compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
|
|
+ reg = <0 0x1100a000 0 0x1000>;
|
|
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
|
|
+ clocks = <&pericfg CLK_PERI_SPI0>;
|
|
+ clock-names = "main";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ nandc: nfi@1100d000 {
|
|
+ compatible = "mediatek,mt2701-nfc";
|
|
+ reg = <0 0x1100d000 0 0x1000>;
|
|
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
|
|
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
|
|
+ clocks = <&pericfg CLK_PERI_NFI>,
|
|
+ <&pericfg CLK_PERI_NFI_PAD>;
|
|
+ clock-names = "nfi_clk", "pad_clk";
|
|
+ status = "disabled";
|
|
+ ecc-engine = <&bch>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ bch: ecc@1100e000 {
|
|
+ compatible = "mediatek,mt2701-ecc";
|
|
+ reg = <0 0x1100e000 0 0x1000>;
|
|
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
|
|
+ clocks = <&pericfg CLK_PERI_NFI_ECC>;
|
|
+ clock-names = "nfiecc_clk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ mmc0: mmc@11230000 {
|
|
+ compatible = "mediatek,mt7623-mmc",
|
|
+ "mediatek,mt8135-mmc";
|
|
+ reg = <0 0x11230000 0 0x1000>;
|
|
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
|
|
+ clocks = <&pericfg CLK_PERI_MSDC30_0>,
|
|
+ <&topckgen CLK_TOP_MSDC30_0_SEL>;
|
|
+ clock-names = "source", "hclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ mmc1: mmc@11240000 {
|
|
+ compatible = "mediatek,mt7623-mmc",
|
|
+ "mediatek,mt8135-mmc";
|
|
+ reg = <0 0x11240000 0 0x1000>;
|
|
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
|
|
+ clocks = <&pericfg CLK_PERI_MSDC30_1>,
|
|
+ <&topckgen CLK_TOP_MSDC30_1_SEL>;
|
|
+ clock-names = "source", "hclk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb1: usb@1a1c0000 {
|
|
+ compatible = "mediatek,mt2701-xhci",
|
|
+ "mediatek,mt8173-xhci";
|
|
+ reg = <0 0x1a1c0000 0 0x1000>,
|
|
+ <0 0x1a1c4700 0 0x0100>;
|
|
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
|
|
+ clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
|
|
+ <&topckgen CLK_TOP_ETHIF_SEL>;
|
|
+ clock-names = "sys_ck", "ethif";
|
|
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
|
|
+ phys = <&phy_port0 PHY_TYPE_USB3>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ u3phy1: usb-phy@1a1c4000 {
|
|
+ compatible = "mediatek,mt2701-u3phy",
|
|
+ "mediatek,mt8173-u3phy";
|
|
+ reg = <0 0x1a1c4000 0 0x0700>;
|
|
+ clocks = <&clk26m>;
|
|
+ clock-names = "u3phya_ref";
|
|
+ #phy-cells = <1>;
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+ status = "disabled";
|
|
+
|
|
+ phy_port0: phy_port0: port@1a1c4800 {
|
|
+ reg = <0 0x1a1c4800 0 0x800>;
|
|
+ #phy-cells = <1>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb2: usb@1a240000 {
|
|
+ compatible = "mediatek,mt2701-xhci",
|
|
+ "mediatek,mt8173-xhci";
|
|
+ reg = <0 0x1a240000 0 0x1000>,
|
|
+ <0 0x1a244700 0 0x0100>;
|
|
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
|
|
+ clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
|
|
+ <&topckgen CLK_TOP_ETHIF_SEL>;
|
|
+ clock-names = "sys_ck", "ethif";
|
|
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
|
|
+ phys = <&u3phy2 0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ u3phy2: usb-phy@1a244000 {
|
|
+ compatible = "mediatek,mt2701-u3phy",
|
|
+ "mediatek,mt8173-u3phy";
|
|
+ reg = <0 0x1a244000 0 0x0700>,
|
|
+ <0 0x1a244800 0 0x0800>;
|
|
+ clocks = <&clk26m>;
|
|
+ clock-names = "u3phya_ref";
|
|
+ #phy-cells = <1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ hifsys: clock-controller@1a000000 {
|
|
+ compatible = "mediatek,mt7623-hifsys",
|
|
+ "mediatek,mt2701-hifsys",
|
|
+ "syscon";
|
|
+ reg = <0 0x1a000000 0 0x1000>;
|
|
+ #clock-cells = <1>;
|
|
+ #reset-cells = <1>;
|
|
+ };
|
|
+
|
|
+ pcie: pcie@1a140000 {
|
|
+ compatible = "mediatek,mt7623-pcie";
|
|
+ device_type = "pci";
|
|
+ reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
|
|
+ <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
|
|
+ <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
|
|
+ <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
|
|
+ reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
|
|
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
|
|
+ <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
|
|
+ <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
|
|
+ interrupt-names = "pcie0", "pcie1", "pcie2";
|
|
+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
|
|
+ clock-names = "pcie";
|
|
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
|
|
+ resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
|
|
+ <&hifsys MT2701_HIFSYS_PCIE1_RST>,
|
|
+ <&hifsys MT2701_HIFSYS_PCIE2_RST>;
|
|
+ reset-names = "pcie0", "pcie1", "pcie2";
|
|
+
|
|
+ mediatek,hifsys = <&hifsys>;
|
|
+
|
|
+ bus-range = <0x00 0xff>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
|
|
+ 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
|
|
+
|
|
+ status = "disabled";
|
|
+
|
|
+ pcie@1,0 {
|
|
+ device_type = "pci";
|
|
+ reg = <0x0800 0 0 0 0>;
|
|
+
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+ };
|
|
+
|
|
+ pcie@2,0{
|
|
+ device_type = "pci";
|
|
+ reg = <0x1000 0 0 0 0>;
|
|
+
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+ };
|
|
+
|
|
+ pcie@3,0{
|
|
+ device_type = "pci";
|
|
+ reg = <0x1800 0 0 0 0>;
|
|
+
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ethsys: syscon@1b000000 {
|
|
+ compatible = "mediatek,mt2701-ethsys", "syscon";
|
|
+ reg = <0 0x1b000000 0 0x1000>;
|
|
+ #reset-cells = <1>;
|
|
+ #clock-cells = <1>;
|
|
+ };
|
|
+
|
|
+ eth: ethernet@1b100000 {
|
|
+ compatible = "mediatek,mt2701-eth";
|
|
+ reg = <0 0x1b100000 0 0x20000>;
|
|
+
|
|
+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
|
|
+ <ðsys CLK_ETHSYS_ESW>,
|
|
+ <ðsys CLK_ETHSYS_GP2>,
|
|
+ <ðsys CLK_ETHSYS_GP1>;
|
|
+ clock-names = "ethif", "esw", "gp2", "gp1";
|
|
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
|
|
+ GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
|
|
+ GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
|
|
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
|
+
|
|
+ resets = <ðsys 6>;
|
|
+ reset-names = "eth";
|
|
+
|
|
+ mediatek,ethsys = <ðsys>;
|
|
+ mediatek,pctl = <&syscfg_pctl_a>;
|
|
+
|
|
+ mediatek,switch = <&gsw>;
|
|
+
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ status = "disabled";
|
|
+
|
|
+ gmac1: mac@0 {
|
|
+ compatible = "mediatek,eth-mac";
|
|
+ reg = <0>;
|
|
+
|
|
+ status = "disabled";
|
|
+
|
|
+ phy-mode = "rgmii";
|
|
+
|
|
+ fixed-link {
|
|
+ speed = <1000>;
|
|
+ full-duplex;
|
|
+ pause;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gmac2: mac@1 {
|
|
+ compatible = "mediatek,eth-mac";
|
|
+ reg = <1>;
|
|
+
|
|
+ status = "disabled";
|
|
+
|
|
+ phy-mode = "rgmii";
|
|
+
|
|
+ fixed-link {
|
|
+ speed = <1000>;
|
|
+ full-duplex;
|
|
+ pause;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ mdio-bus {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ phy5: ethernet-phy@5 {
|
|
+ reg = <5>;
|
|
+ phy-mode = "rgmii-rxid";
|
|
+ };
|
|
+
|
|
+ phy1f: ethernet-phy@1f {
|
|
+ reg = <0x1f>;
|
|
+ phy-mode = "rgmii";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gsw: switch@1b100000 {
|
|
+ compatible = "mediatek,mt7623-gsw";
|
|
+ interrupt-parent = <&pio>;
|
|
+ interrupts = <168 IRQ_TYPE_EDGE_RISING>;
|
|
+ resets = <ðsys 2>;
|
|
+ reset-names = "eth";
|
|
+ clocks = <&apmixedsys CLK_APMIXED_TRGPLL>;
|
|
+ clock-names = "trgpll";
|
|
+ mt7530-supply = <&mt6323_vpa_reg>;
|
|
+ mediatek,pctl-regmap = <&syscfg_pctl_a>;
|
|
+ mediatek,ethsys = <ðsys>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+};
|
|
--- a/arch/arm/mach-mediatek/Kconfig
|
|
+++ b/arch/arm/mach-mediatek/Kconfig
|
|
@@ -21,6 +21,10 @@ config MACH_MT6592
|
|
bool "MediaTek MT6592 SoCs support"
|
|
default ARCH_MEDIATEK
|
|
|
|
+config MACH_MT7623
|
|
+ bool "MediaTek MT7623 SoCs support"
|
|
+ default ARCH_MEDIATEK
|
|
+
|
|
config MACH_MT8127
|
|
bool "MediaTek MT8127 SoCs support"
|
|
default ARCH_MEDIATEK
|
|
--- a/arch/arm/mach-mediatek/mediatek.c
|
|
+++ b/arch/arm/mach-mediatek/mediatek.c
|
|
@@ -46,6 +46,7 @@ static void __init mediatek_timer_init(v
|
|
static const char * const mediatek_board_dt_compat[] = {
|
|
"mediatek,mt6589",
|
|
"mediatek,mt6592",
|
|
+ "mediatek,mt7623",
|
|
"mediatek,mt8127",
|
|
"mediatek,mt8135",
|
|
NULL,
|