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616 lines
15 KiB
Plaintext
616 lines
15 KiB
Plaintext
/*
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* Copyright (c) 2016 MediaTek Inc.
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* Author: John Crispin <blogic@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt2701-clk.h>
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#include <dt-bindings/power/mt2701-power.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset-controller/mt2701-resets.h>
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#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
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#include "skeleton64.dtsi"
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/ {
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compatible = "mediatek,mt7623";
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interrupt-parent = <&sysirq>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt6589-smp";
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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clocks = <&infracfg CLK_INFRA_CPUSEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points = <
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598000 1150000
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747500 1150000
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1040000 1150000
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1196000 1200000
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1300000 1300000
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>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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clocks = <&infracfg CLK_INFRA_CPUSEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points = <
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598000 1150000
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747500 1150000
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1040000 1150000
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1196000 1200000
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1300000 1300000
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>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x2>;
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clocks = <&infracfg CLK_INFRA_CPUSEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points = <
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598000 1150000
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747500 1150000
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1040000 1150000
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1196000 1200000
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1300000 1300000
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>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x3>;
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clocks = <&infracfg CLK_INFRA_CPUSEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points = <
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598000 1150000
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747500 1150000
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1040000 1150000
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1196000 1200000
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1300000 1300000
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>;
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};
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};
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system_clk: dummy13m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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};
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rtc_clk: dummy32k {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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clock-output-names = "clk32k";
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};
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clk26m: dummy26m {
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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#clock-cells = <0>;
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clock-output-names = "clk26m";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <13000000>;
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arm,cpu-registers-not-fw-configured;
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};
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topckgen: power-controller@10000000 {
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compatible = "mediatek,mt7623-topckgen",
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"mediatek,mt2701-topckgen",
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"syscon";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: power-controller@10001000 {
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compatible = "mediatek,mt7623-infracfg",
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"mediatek,mt2701-infracfg",
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"syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pericfg: pericfg@10003000 {
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compatible = "mediatek,mt7623-pericfg",
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"mediatek,mt2701-pericfg",
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"syscon";
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reg = <0 0x10003000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt7623-pinctrl";
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reg = <0 0x1000b000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>;
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pins-are-numbered;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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};
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syscfg_pctl_a: syscfg@10005000 {
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compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
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reg = <0 0x10005000 0 0x1000>;
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};
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scpsys: scpsys@10006000 {
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#power-domain-cells = <1>;
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compatible = "mediatek,mt7623-scpsys",
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"mediatek,mt2701-scpsys";
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reg = <0 0x10006000 0 0x1000>;
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infracfg = <&infracfg>;
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clocks = <&clk26m>,
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<&topckgen CLK_TOP_MM_SEL>;
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clock-names = "mfg", "mm";
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};
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watchdog: watchdog@10007000 {
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compatible = "mediatek,mt7623-wdt",
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"mediatek,mt6589-wdt";
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reg = <0 0x10007000 0 0x100>;
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};
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timer: timer@10008000 {
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compatible = "mediatek,mt7623-timer",
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"mediatek,mt6577-timer";
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reg = <0 0x10008000 0 0x80>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&system_clk>, <&rtc_clk>;
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clock-names = "system-clk", "rtc-clk";
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};
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pwrap: pwrap@1000d000 {
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compatible = "mediatek,mt7623-pwrap",
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"mediatek,mt2701-pwrap";
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reg = <0 0x1000d000 0 0x1000>;
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reg-names = "pwrap";
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
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reset-names = "pwrap";
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clocks = <&infracfg CLK_INFRA_PMICSPI>,
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<&infracfg CLK_INFRA_PMICWRAP>;
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clock-names = "spi", "wrap";
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};
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sysirq: interrupt-controller@10200100 {
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compatible = "mediatek,mt7623-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10200100 0 0x1c>;
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};
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apmixedsys: apmixedsys@10209000 {
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compatible = "mediatek,mt7623-apmixedsys",
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"mediatek,mt2701-apmixedsys";
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reg = <0 0x10209000 0 0x1000>;
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#clock-cells = <1>;
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};
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gic: interrupt-controller@10211000 {
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compatible = "arm,cortex-a7-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10211000 0 0x1000>,
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<0 0x10212000 0 0x1000>,
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<0 0x10214000 0 0x2000>,
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<0 0x10216000 0 0x2000>;
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};
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i2c0: i2c@11007000 {
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compatible = "mediatek,mt7623-i2c",
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"mediatek,mt6577-i2c";
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reg = <0 0x11007000 0 0x70>,
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<0 0x11000200 0 0x80>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C0>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@11008000 {
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compatible = "mediatek,mt7623-i2c",
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"mediatek,mt6577-i2c";
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reg = <0 0x11008000 0 0x70>,
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<0 0x11000280 0 0x80>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C1>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@11009000 {
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compatible = "mediatek,mt7623-i2c",
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"mediatek,mt6577-i2c";
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reg = <0 0x11009000 0 0x70>,
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<0 0x11000300 0 0x80>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C2>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt7623-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART0_SEL>,
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<&pericfg CLK_PERI_UART0>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt7623-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART1_SEL>,
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<&pericfg CLK_PERI_UART1>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt7623-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART2_SEL>,
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<&pericfg CLK_PERI_UART2>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart3: serial@11005000 {
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compatible = "mediatek,mt7623-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11005000 0 0x400>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART3_SEL>,
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<&pericfg CLK_PERI_UART3>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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pwm: pwm@11006000 {
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compatible = "mediatek,mt7623-pwm";
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reg = <0 0x11006000 0 0x1000>;
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resets = <&pericfg MT2701_PERI_PWM_SW_RST>;
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reset-names = "pwm";
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#pwm-cells = <2>;
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clocks = <&topckgen CLK_TOP_PWM_SEL>,
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<&pericfg CLK_PERI_PWM>,
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<&pericfg CLK_PERI_PWM1>,
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<&pericfg CLK_PERI_PWM2>,
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<&pericfg CLK_PERI_PWM3>,
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<&pericfg CLK_PERI_PWM4>,
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<&pericfg CLK_PERI_PWM5>;
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clock-names = "top", "main", "pwm1", "pwm2",
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"pwm3", "pwm4", "pwm5";
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status = "disabled";
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};
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spi: spi@1100a000 {
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compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
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reg = <0 0x1100a000 0 0x1000>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_SPI0>;
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clock-names = "main";
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status = "disabled";
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};
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nandc: nfi@1100d000 {
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compatible = "mediatek,mt2701-nfc";
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reg = <0 0x1100d000 0 0x1000>;
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power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_NFI>,
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<&pericfg CLK_PERI_NFI_PAD>;
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clock-names = "nfi_clk", "pad_clk";
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status = "disabled";
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ecc-engine = <&bch>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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bch: ecc@1100e000 {
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compatible = "mediatek,mt2701-ecc";
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reg = <0 0x1100e000 0 0x1000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_NFI_ECC>;
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clock-names = "nfiecc_clk";
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status = "disabled";
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};
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt7623-mmc",
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"mediatek,mt8135-mmc";
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reg = <0 0x11230000 0 0x1000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_MSDC30_0>,
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<&topckgen CLK_TOP_MSDC30_0_SEL>;
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clock-names = "source", "hclk";
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status = "disabled";
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};
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mmc1: mmc@11240000 {
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compatible = "mediatek,mt7623-mmc",
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"mediatek,mt8135-mmc";
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reg = <0 0x11240000 0 0x1000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_MSDC30_1>,
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<&topckgen CLK_TOP_MSDC30_1_SEL>;
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clock-names = "source", "hclk";
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status = "disabled";
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};
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usb1: usb@1a1c0000 {
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compatible = "mediatek,mt2701-xhci",
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"mediatek,mt8173-xhci";
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reg = <0 0x1a1c0000 0 0x1000>,
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<0 0x1a1c4700 0 0x0100>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
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<&topckgen CLK_TOP_ETHIF_SEL>;
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clock-names = "sys_ck", "ethif";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
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phys = <&phy_port0 PHY_TYPE_USB3>;
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status = "disabled";
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};
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u3phy1: usb-phy@1a1c4000 {
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compatible = "mediatek,mt2701-u3phy",
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"mediatek,mt8173-u3phy";
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reg = <0 0x1a1c4000 0 0x0700>;
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clocks = <&clk26m>;
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clock-names = "u3phya_ref";
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#phy-cells = <1>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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phy_port0: phy_port0: port@1a1c4800 {
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reg = <0 0x1a1c4800 0 0x800>;
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#phy-cells = <1>;
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status = "okay";
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};
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};
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usb2: usb@1a240000 {
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compatible = "mediatek,mt2701-xhci",
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"mediatek,mt8173-xhci";
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reg = <0 0x1a240000 0 0x1000>,
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<0 0x1a244700 0 0x0100>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
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<&topckgen CLK_TOP_ETHIF_SEL>;
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clock-names = "sys_ck", "ethif";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
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phys = <&u3phy2 0>;
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status = "disabled";
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};
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u3phy2: usb-phy@1a244000 {
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compatible = "mediatek,mt2701-u3phy",
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"mediatek,mt8173-u3phy";
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reg = <0 0x1a244000 0 0x0700>,
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<0 0x1a244800 0 0x0800>;
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clocks = <&clk26m>;
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clock-names = "u3phya_ref";
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#phy-cells = <1>;
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status = "disabled";
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};
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hifsys: clock-controller@1a000000 {
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compatible = "mediatek,mt7623-hifsys",
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"mediatek,mt2701-hifsys",
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"syscon";
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reg = <0 0x1a000000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pcie: pcie@1a140000 {
|
|
compatible = "mediatek,mt7623-pcie";
|
|
device_type = "pci";
|
|
reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
|
|
<0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
|
|
<0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
|
|
<0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
|
|
reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
|
|
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-names = "pcie0", "pcie1", "pcie2";
|
|
clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
|
|
clock-names = "pcie";
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
|
|
resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
|
|
<&hifsys MT2701_HIFSYS_PCIE1_RST>,
|
|
<&hifsys MT2701_HIFSYS_PCIE2_RST>;
|
|
reset-names = "pcie0", "pcie1", "pcie2";
|
|
|
|
mediatek,hifsys = <&hifsys>;
|
|
|
|
bus-range = <0x00 0xff>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
|
|
0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
|
|
|
|
status = "disabled";
|
|
|
|
pcie@1,0 {
|
|
device_type = "pci";
|
|
reg = <0x0800 0 0 0 0>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
|
|
pcie@2,0{
|
|
device_type = "pci";
|
|
reg = <0x1000 0 0 0 0>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
|
|
pcie@3,0{
|
|
device_type = "pci";
|
|
reg = <0x1800 0 0 0 0>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
};
|
|
|
|
ethsys: syscon@1b000000 {
|
|
compatible = "mediatek,mt2701-ethsys", "syscon";
|
|
reg = <0 0x1b000000 0 0x1000>;
|
|
#reset-cells = <1>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
eth: ethernet@1b100000 {
|
|
compatible = "mediatek,mt2701-eth";
|
|
reg = <0 0x1b100000 0 0x20000>;
|
|
|
|
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
|
|
<ðsys CLK_ETHSYS_ESW>,
|
|
<ðsys CLK_ETHSYS_GP2>,
|
|
<ðsys CLK_ETHSYS_GP1>;
|
|
clock-names = "ethif", "esw", "gp2", "gp1";
|
|
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
|
|
GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
|
|
GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
|
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
|
|
|
resets = <ðsys 6>;
|
|
reset-names = "eth";
|
|
|
|
mediatek,ethsys = <ðsys>;
|
|
mediatek,pctl = <&syscfg_pctl_a>;
|
|
|
|
mediatek,switch = <&gsw>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
gmac1: mac@0 {
|
|
compatible = "mediatek,eth-mac";
|
|
reg = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
phy-mode = "rgmii";
|
|
|
|
fixed-link {
|
|
speed = <1000>;
|
|
full-duplex;
|
|
pause;
|
|
};
|
|
};
|
|
|
|
gmac2: mac@1 {
|
|
compatible = "mediatek,eth-mac";
|
|
reg = <1>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
mdio-bus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
phy5: ethernet-phy@5 {
|
|
reg = <5>;
|
|
phy-mode = "rgmii-rxid";
|
|
};
|
|
|
|
phy1f: ethernet-phy@1f {
|
|
reg = <0x1f>;
|
|
phy-mode = "rgmii";
|
|
};
|
|
};
|
|
};
|
|
|
|
gsw: switch@1b100000 {
|
|
compatible = "mediatek,mt7623-gsw";
|
|
interrupt-parent = <&pio>;
|
|
interrupts = <168 IRQ_TYPE_EDGE_RISING>;
|
|
resets = <ðsys 2>;
|
|
reset-names = "eth";
|
|
clocks = <&apmixedsys CLK_APMIXED_TRGPLL>;
|
|
clock-names = "trgpll";
|
|
mt7530-supply = <&mt6323_vpa_reg>;
|
|
mediatek,pctl-regmap = <&syscfg_pctl_a>;
|
|
mediatek,ethsys = <ðsys>;
|
|
status = "disabled";
|
|
};
|
|
};
|