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974 lines
32 KiB
Diff
974 lines
32 KiB
Diff
--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
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+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
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@@ -9063,6 +9063,943 @@ restore_value:
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rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
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}
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+static void rt2800_rf_configstore(struct rt2x00_dev *rt2x00dev, rf_reg_pair rf_reg_record[][13], u8 chain)
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+{
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+ u8 rfvalue = 0;
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+
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+ if (chain == CHAIN_0) {
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
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+ rf_reg_record[CHAIN_0][0].bank = 0;
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+ rf_reg_record[CHAIN_0][0].reg = 1;
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+ rf_reg_record[CHAIN_0][0].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
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+ rf_reg_record[CHAIN_0][1].bank = 0;
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+ rf_reg_record[CHAIN_0][1].reg = 2;
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+ rf_reg_record[CHAIN_0][1].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
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+ rf_reg_record[CHAIN_0][2].bank = 0;
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+ rf_reg_record[CHAIN_0][2].reg = 35;
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+ rf_reg_record[CHAIN_0][2].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
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+ rf_reg_record[CHAIN_0][3].bank = 0;
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+ rf_reg_record[CHAIN_0][3].reg = 42;
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+ rf_reg_record[CHAIN_0][3].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
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+ rf_reg_record[CHAIN_0][4].bank = 4;
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+ rf_reg_record[CHAIN_0][4].reg = 0;
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+ rf_reg_record[CHAIN_0][4].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 2);
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+ rf_reg_record[CHAIN_0][5].bank = 4;
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+ rf_reg_record[CHAIN_0][5].reg = 2;
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+ rf_reg_record[CHAIN_0][5].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 34);
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+ rf_reg_record[CHAIN_0][6].bank = 4;
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+ rf_reg_record[CHAIN_0][6].reg = 34;
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+ rf_reg_record[CHAIN_0][6].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
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+ rf_reg_record[CHAIN_0][7].bank = 5;
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+ rf_reg_record[CHAIN_0][7].reg = 3;
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+ rf_reg_record[CHAIN_0][7].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
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+ rf_reg_record[CHAIN_0][8].bank = 5;
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+ rf_reg_record[CHAIN_0][8].reg = 4;
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+ rf_reg_record[CHAIN_0][8].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
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+ rf_reg_record[CHAIN_0][9].bank = 5;
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+ rf_reg_record[CHAIN_0][9].reg = 17;
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+ rf_reg_record[CHAIN_0][9].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
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+ rf_reg_record[CHAIN_0][10].bank = 5;
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+ rf_reg_record[CHAIN_0][10].reg = 18;
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+ rf_reg_record[CHAIN_0][10].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
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+ rf_reg_record[CHAIN_0][11].bank = 5;
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+ rf_reg_record[CHAIN_0][11].reg = 19;
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+ rf_reg_record[CHAIN_0][11].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
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+ rf_reg_record[CHAIN_0][12].bank = 5;
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+ rf_reg_record[CHAIN_0][12].reg = 20;
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+ rf_reg_record[CHAIN_0][12].value = rfvalue;
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+ } else if (chain == CHAIN_1) {
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
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+ rf_reg_record[CHAIN_1][0].bank = 0;
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+ rf_reg_record[CHAIN_1][0].reg = 1;
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+ rf_reg_record[CHAIN_1][0].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
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+ rf_reg_record[CHAIN_1][1].bank = 0;
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+ rf_reg_record[CHAIN_1][1].reg = 2;
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+ rf_reg_record[CHAIN_1][1].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
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+ rf_reg_record[CHAIN_1][2].bank = 0;
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+ rf_reg_record[CHAIN_1][2].reg = 35;
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+ rf_reg_record[CHAIN_1][2].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
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+ rf_reg_record[CHAIN_1][3].bank = 0;
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+ rf_reg_record[CHAIN_1][3].reg = 42;
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+ rf_reg_record[CHAIN_1][3].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
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+ rf_reg_record[CHAIN_1][4].bank = 6;
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+ rf_reg_record[CHAIN_1][4].reg = 0;
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+ rf_reg_record[CHAIN_1][4].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 2);
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+ rf_reg_record[CHAIN_1][5].bank = 6;
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+ rf_reg_record[CHAIN_1][5].reg = 2;
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+ rf_reg_record[CHAIN_1][5].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 34);
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+ rf_reg_record[CHAIN_1][6].bank = 6;
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+ rf_reg_record[CHAIN_1][6].reg = 34;
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+ rf_reg_record[CHAIN_1][6].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
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+ rf_reg_record[CHAIN_1][7].bank = 7;
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+ rf_reg_record[CHAIN_1][7].reg = 3;
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+ rf_reg_record[CHAIN_1][7].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
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+ rf_reg_record[CHAIN_1][8].bank = 7;
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+ rf_reg_record[CHAIN_1][8].reg = 4;
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+ rf_reg_record[CHAIN_1][8].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
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+ rf_reg_record[CHAIN_1][9].bank = 7;
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+ rf_reg_record[CHAIN_1][9].reg = 17;
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+ rf_reg_record[CHAIN_1][9].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
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+ rf_reg_record[CHAIN_1][10].bank = 7;
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+ rf_reg_record[CHAIN_1][10].reg = 18;
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+ rf_reg_record[CHAIN_1][10].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
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+ rf_reg_record[CHAIN_1][11].bank = 7;
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+ rf_reg_record[CHAIN_1][11].reg = 19;
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+ rf_reg_record[CHAIN_1][11].value = rfvalue;
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+ rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
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+ rf_reg_record[CHAIN_1][12].bank = 7;
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+ rf_reg_record[CHAIN_1][12].reg = 20;
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+ rf_reg_record[CHAIN_1][12].value = rfvalue;
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+ } else {
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+ rt2x00_warn(rt2x00dev, "Unknown chain = %u\n", chain);
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+ return;
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+ }
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+
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+ return;
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+}
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+
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+static void rt2800_rf_configrecover(struct rt2x00_dev *rt2x00dev, rf_reg_pair rf_record[][13])
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+{
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+ u8 chain_index = 0, record_index = 0;
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+ u8 bank = 0, rf_register = 0, value = 0;
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+
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+ for (chain_index = 0; chain_index < 2; chain_index++) {
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+ for (record_index = 0; record_index < 13; record_index++) {
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+ bank = rf_record[chain_index][record_index].bank;
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+ rf_register = rf_record[chain_index][record_index].reg;
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+ value = rf_record[chain_index][record_index].value;
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+ rt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value);
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+ rt2x00_dbg(rt2x00dev, "bank: %d, rf_register: %d, value: %x\n", bank, rf_register, value);
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+ }
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+ }
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+
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+ return;
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+}
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+
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+static void rt2800_setbbptonegenerator(struct rt2x00_dev *rt2x00dev)
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+{
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+ rt2800_bbp_write(rt2x00dev, 158, 0xAA);
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+ rt2800_bbp_write(rt2x00dev, 159, 0x00);
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+
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+ rt2800_bbp_write(rt2x00dev, 158, 0xAB);
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+ rt2800_bbp_write(rt2x00dev, 159, 0x0A);
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+
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+ rt2800_bbp_write(rt2x00dev, 158, 0xAC);
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+ rt2800_bbp_write(rt2x00dev, 159, 0x3F);
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+
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+ rt2800_bbp_write(rt2x00dev, 158, 0xAD);
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+ rt2800_bbp_write(rt2x00dev, 159, 0x3F);
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+
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+ rt2800_bbp_write(rt2x00dev, 244, 0x40);
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+
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+ return;
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+}
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+
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+static u32 rt2800_do_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx, u8 read_neg)
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+{
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+ u32 macvalue = 0;
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+ int fftout_i = 0, fftout_q = 0;
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+ u32 ptmp=0, pint = 0;
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+ u8 bbp = 0;
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+ u8 tidxi;
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+
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+ rt2800_bbp_write(rt2x00dev, 158, 0x00);
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+ rt2800_bbp_write(rt2x00dev, 159, 0x9b);
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+
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+ bbp = 0x9b;
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+
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+ while (bbp == 0x9b) {
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+ udelay(10);
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+ bbp = rt2800_bbp_read(rt2x00dev, 159);
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+ bbp = bbp & 0xff;
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+ }
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+
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+ rt2800_bbp_write(rt2x00dev, 158, 0xba);
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+ rt2800_bbp_write(rt2x00dev, 159, tidx);
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+ rt2800_bbp_write(rt2x00dev, 159, tidx);
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+ rt2800_bbp_write(rt2x00dev, 159, tidx);
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+
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+ macvalue = rt2800_register_read(rt2x00dev, 0x057C);
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+
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+ fftout_i = (macvalue >> 16);
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+ fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
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+ fftout_q = (macvalue & 0xffff);
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+ fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
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+ ptmp = (fftout_i * fftout_i);
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+ ptmp = ptmp + (fftout_q * fftout_q);
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+ pint = ptmp;
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+ rt2x00_dbg(rt2x00dev, "I = %d, Q = %d, power = %x\n", fftout_i, fftout_q, pint);
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+ if (read_neg) {
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+ pint = pint >> 1;
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+ tidxi = 0x40 - tidx;
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+ tidxi = tidxi & 0x3f;
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+
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+ rt2800_bbp_write(rt2x00dev, 158, 0xba);
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+ rt2800_bbp_write(rt2x00dev, 159, tidxi);
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+ rt2800_bbp_write(rt2x00dev, 159, tidxi);
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+ rt2800_bbp_write(rt2x00dev, 159, tidxi);
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+
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+ macvalue = rt2800_register_read(rt2x00dev, 0x057C);
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+
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+ fftout_i = (macvalue >> 16);
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+ fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
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+ fftout_q = (macvalue & 0xffff);
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+ fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
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+ ptmp = (fftout_i * fftout_i);
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+ ptmp = ptmp + (fftout_q * fftout_q);
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+ ptmp = ptmp >> 1;
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+ pint = pint + ptmp;
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+ }
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+
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+ return pint;
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+}
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+
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+static u32 rt2800_read_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx) {
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+ u32 macvalue = 0;
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+ int fftout_i = 0, fftout_q = 0;
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+ u32 ptmp=0, pint = 0;
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+
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+ rt2800_bbp_write(rt2x00dev, 158, 0xBA);
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+ rt2800_bbp_write(rt2x00dev, 159, tidx);
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+ rt2800_bbp_write(rt2x00dev, 159, tidx);
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+ rt2800_bbp_write(rt2x00dev, 159, tidx);
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+
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+ macvalue = rt2800_register_read(rt2x00dev, 0x057C);
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+
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+ fftout_i = (macvalue >> 16);
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+ fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
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+ fftout_q = (macvalue & 0xffff);
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+ fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
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+ ptmp = (fftout_i * fftout_i);
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+ ptmp = ptmp + (fftout_q * fftout_q);
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+ pint = ptmp;
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+ rt2x00_info(rt2x00dev, "I = %d, Q = %d, power = %x\n", fftout_i, fftout_q, pint);
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+
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+ return pint;
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+}
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+
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+static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc)
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+{
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+ u8 bbp = 0;
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+
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+ rt2800_bbp_write(rt2x00dev, 158, 0xb0);
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+ bbp = alc | 0x80;
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+ rt2800_bbp_write(rt2x00dev, 159, bbp);
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+
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+ if (ch_idx == 0)
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+ bbp = (iorq == 0) ? 0xb1: 0xb2;
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+ else
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+ bbp = (iorq == 0) ? 0xb8: 0xb9;
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+
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+ rt2800_bbp_write(rt2x00dev, 158, bbp);
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+ bbp = dc;
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+ rt2800_bbp_write(rt2x00dev, 159, bbp);
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+
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+ return;
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+}
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+
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+static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2])
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+{
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+ u32 p0 = 0, p1 = 0, pf = 0;
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+ char idx0 = 0, idx1 = 0;
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+ u8 idxf[] = {0x00, 0x00};
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+ u8 ibit = 0x20;
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+ u8 iorq;
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+ char bidx;
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+
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+ rt2800_bbp_write(rt2x00dev, 158, 0xb0);
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+ rt2800_bbp_write(rt2x00dev, 159, 0x80);
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+
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+ for (bidx = 5; bidx >= 0; bidx--) {
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+ for (iorq = 0; iorq <= 1; iorq++) {
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+ rt2x00_dbg(rt2x00dev, "\n========================================================\n");
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+
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+ if (idxf[iorq] == 0x20) {
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+ idx0 = 0x20;
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+ p0 = pf;
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+ } else {
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+ idx0 = idxf[iorq] - ibit;
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+ idx0 = idx0 & 0x3F;
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+ rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx0);
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+ p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
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+ }
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+
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+ idx1 = idxf[iorq] + ((bidx == 5) ? 0 : ibit);
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+ idx1 = idx1 & 0x3F;
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+ rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx1);
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+ p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
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+
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+ rt2x00_dbg(rt2x00dev, "alc=%u, IorQ=%u, idx_final=%2x\n", alc_idx, iorq, idxf[iorq]);
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+ rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x !\n", p0, p1, pf, idx0, idx1, ibit);
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+
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+ if ((bidx != 5) && (pf <= p0) && (pf < p1)) {
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+ pf = pf;
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+ idxf[iorq] = idxf[iorq];
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+ } else if (p0 < p1) {
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+ pf = p0;
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+ idxf[iorq] = idx0 & 0x3F;
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+ } else {
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+ pf = p1;
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+ idxf[iorq] = idx1 & 0x3F;
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+ }
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+ rt2x00_dbg(rt2x00dev, "IorQ=%u, idx_final[%u]:%x, pf:%8x\n", iorq, iorq, idxf[iorq], pf);
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+
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+ rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idxf[iorq]);
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+
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+ }
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+ ibit = ibit >> 1;
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+ }
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+ dc_result[ch_idx][alc_idx][0] = idxf[0];
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+ dc_result[ch_idx][alc_idx][1] = idxf[1];
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+
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+ return;
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+}
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+
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+static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes)
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+{
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+ u32 p0 = 0, p1 = 0, pf = 0;
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+ char perr = 0, gerr = 0, iq_err = 0;
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+ char pef = 0, gef = 0;
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+ char psta, pend;
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+ char gsta, gend;
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+
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+ u8 ibit = 0x20;
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+ u8 first_search = 0x00, touch_neg_max = 0x00;
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+ char idx0 = 0, idx1 = 0;
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+ u8 gop;
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+ u8 bbp = 0;
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+ char bidx;
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+
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+ rt2x00_info(rt2x00dev, "IQCalibration Start!\n");
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+ for (bidx = 5; bidx >= 1; bidx--) {
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+ for (gop = 0; gop < 2; gop++) {
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+ rt2x00_dbg(rt2x00dev, "\n========================================================\n");
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+
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+ if ((gop == 1) || (bidx < 4)) {
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+ if (gop == 0)
|
|
+ iq_err = gerr;
|
|
+ else
|
|
+ iq_err = perr;
|
|
+
|
|
+ first_search = (gop == 0) ? (bidx == 3) : (bidx == 5);
|
|
+ touch_neg_max = (gop) ? ((iq_err & 0x0F) == 0x08) : ((iq_err & 0x3F) == 0x20);
|
|
+
|
|
+ if (touch_neg_max) {
|
|
+ p0 = pf;
|
|
+ idx0 = iq_err;
|
|
+ } else {
|
|
+ idx0 = iq_err - ibit;
|
|
+ bbp = (ch_idx == 0) ? ((gop == 0) ? 0x28 : 0x29): ((gop == 0) ? 0x46 : 0x47);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 158, bbp);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, idx0);
|
|
+
|
|
+ p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
|
|
+ }
|
|
+
|
|
+ idx1 = iq_err + (first_search ? 0 : ibit);
|
|
+ idx1 = (gop == 0) ? (idx1 & 0x0F) : (idx1 & 0x3F);
|
|
+
|
|
+ bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : (gop == 0) ? 0x46 : 0x47;
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 158, bbp);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, idx1);
|
|
+
|
|
+ p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
|
|
+
|
|
+ rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pwer_final=%x, idx0=%x, idx1=%x, iq_err=%x, gop=%d, ibit=%x !\n", p0, p1, pf, idx0, idx1, iq_err, gop, ibit);
|
|
+
|
|
+ if ((!first_search) && (pf <= p0) && (pf < p1)) {
|
|
+ pf = pf;
|
|
+ } else if (p0 < p1) {
|
|
+ pf = p0;
|
|
+ iq_err = idx0;
|
|
+ } else {
|
|
+ pf = p1;
|
|
+ iq_err = idx1;
|
|
+ }
|
|
+
|
|
+ bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : (gop == 0) ? 0x46 : 0x47;
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 158, bbp);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, iq_err);
|
|
+
|
|
+ if (gop == 0)
|
|
+ gerr = iq_err;
|
|
+ else
|
|
+ perr = iq_err;
|
|
+
|
|
+ rt2x00_dbg(rt2x00dev, "IQCalibration pf=%8x (%2x, %2x) !\n", pf, gerr & 0x0F, perr & 0x3F);
|
|
+
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (bidx > 0)
|
|
+ ibit = (ibit >> 1);
|
|
+ }
|
|
+ gerr = (gerr & 0x08) ? (gerr & 0x0F) - 0x10 : (gerr & 0x0F);
|
|
+ perr = (perr & 0x20) ? (perr & 0x3F) - 0x40 : (perr & 0x3F);
|
|
+
|
|
+ gerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr;
|
|
+ gsta = gerr - 1;
|
|
+ gend = gerr + 2;
|
|
+
|
|
+ perr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr;
|
|
+ psta = perr - 1;
|
|
+ pend = perr + 2;
|
|
+
|
|
+ for (gef = gsta; gef <= gend; gef = gef + 1)
|
|
+ for (pef = psta; pef <= pend; pef = pef + 1) {
|
|
+ bbp = (ch_idx == 0) ? 0x28 : 0x46;
|
|
+ rt2800_bbp_write(rt2x00dev, 158, bbp);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, gef & 0x0F);
|
|
+
|
|
+ bbp = (ch_idx == 0) ? 0x29 : 0x47;
|
|
+ rt2800_bbp_write(rt2x00dev, 158, bbp);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, pef & 0x3F);
|
|
+
|
|
+ p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
|
|
+ if ((gef == gsta) && (pef == psta)) {
|
|
+ pf = p1;
|
|
+ gerr = gef;
|
|
+ perr = pef;
|
|
+ }
|
|
+ else if (pf > p1){
|
|
+ pf = p1;
|
|
+ gerr = gef;
|
|
+ perr = pef;
|
|
+ }
|
|
+ rt2x00_dbg(rt2x00dev, "Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n", p1, pf, gef & 0x0F, pef & 0x3F);
|
|
+ }
|
|
+
|
|
+ ges[ch_idx] = gerr & 0x0F;
|
|
+ pes[ch_idx] = perr & 0x3F;
|
|
+
|
|
+ rt2x00_info(rt2x00dev, "IQCalibration Done! CH = %u, (gain=%2x, phase=%2x)\n", ch_idx, gerr & 0x0F, perr & 0x3F);
|
|
+
|
|
+ return;
|
|
+}
|
|
+
|
|
+static void rt2800_rf_aux_tx0_loopback(struct rt2x00_dev *rt2x00dev)
|
|
+{
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x21);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x10);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x1b);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, 0x81);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 2, 0x81);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 34, 0xee);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, 0x2d);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x2d);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xd7);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0xa2);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
|
|
+}
|
|
+
|
|
+static void rt2800_rf_aux_tx1_loopback(struct rt2x00_dev *rt2x00dev)
|
|
+{
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x22);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x20);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x4b);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, 0x81);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 2, 0x81);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 34, 0xee);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, 0x2d);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, 0x2d);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, 0x80);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, 0xd7);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, 0xa2);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, 0x20);
|
|
+}
|
|
+
|
|
+void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
|
|
+{
|
|
+ rf_reg_pair rf_store[CHAIN_NUM][13];
|
|
+ u32 macorg1 = 0;
|
|
+ u32 macorg2 = 0;
|
|
+ u32 macorg3 = 0;
|
|
+ u32 macorg4 = 0;
|
|
+ u32 macorg5 = 0;
|
|
+ u32 orig528 = 0;
|
|
+ u32 orig52c = 0;
|
|
+
|
|
+ u32 savemacsysctrl = 0, mtxcycle = 0;
|
|
+ u32 macvalue = 0;
|
|
+ u32 mac13b8 = 0;
|
|
+ u32 p0 = 0, p1 = 0;
|
|
+ u32 p0_idx10 = 0, p1_idx10 = 0;
|
|
+
|
|
+ u8 rfvalue;
|
|
+ u8 loft_dc_search_result[CHAIN_NUM][RF_ALC_NUM][2];
|
|
+ u8 ger[CHAIN_NUM], per[CHAIN_NUM];
|
|
+ u8 rf_gain[] = {0x00, 0x01, 0x02, 0x04, 0x08, 0x0c};
|
|
+ u8 rfvga_gain_table[] = {0x24, 0x25, 0x26, 0x27, 0x28, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3F};
|
|
+
|
|
+ u8 vga_gain[] = {14, 14};
|
|
+ u8 bbp_2324gain[] = {0x16, 0x14, 0x12, 0x10, 0x0c, 0x08};
|
|
+ u8 bbp = 0, ch_idx = 0, rf_alc_idx = 0, idx = 0;
|
|
+ u8 bbpr30, rfb0r39, rfb0r42;
|
|
+ u8 bbpr1;
|
|
+ u8 bbpr4;
|
|
+ u8 bbpr241, bbpr242;
|
|
+ u8 count_step;
|
|
+
|
|
+ savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
|
|
+ macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
|
|
+ macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
|
|
+ macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
|
|
+ macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
|
|
+ macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
|
|
+ mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
|
|
+ orig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
|
|
+ orig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
|
|
+
|
|
+ macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
|
|
+ macvalue &= (~0x04);
|
|
+ rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
|
|
+
|
|
+ for (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {
|
|
+ macvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
|
|
+ if (macvalue & 0x01)
|
|
+ udelay(50);
|
|
+ else
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
|
|
+ macvalue &= (~0x08);
|
|
+ rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
|
|
+
|
|
+ for (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {
|
|
+ macvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
|
|
+ if (macvalue & 0x02)
|
|
+ udelay(50);
|
|
+ else
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ for (ch_idx = 0; ch_idx < 2; ch_idx++) {
|
|
+ rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
|
|
+ }
|
|
+
|
|
+ bbpr30 = rt2800_bbp_read(rt2x00dev, 30);
|
|
+ rfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39);
|
|
+ rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 30, 0x1F);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 23, 0x00);
|
|
+ rt2800_bbp_write(rt2x00dev, 24, 0x00);
|
|
+
|
|
+ rt2800_setbbptonegenerator(rt2x00dev);
|
|
+
|
|
+ for (ch_idx = 0; ch_idx < 2; ch_idx ++) {
|
|
+ rt2800_bbp_write(rt2x00dev, 23, 0x00);
|
|
+ rt2800_bbp_write(rt2x00dev, 24, 0x00);
|
|
+ rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
|
|
+ rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
|
|
+ rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
|
|
+ rt2800_register_write(rt2x00dev, 0x13b8, 0x10);
|
|
+ udelay(1);
|
|
+
|
|
+ if (ch_idx == 0) {
|
|
+ rt2800_rf_aux_tx0_loopback(rt2x00dev);
|
|
+ } else {
|
|
+ rt2800_rf_aux_tx1_loopback(rt2x00dev);
|
|
+ }
|
|
+ udelay(1);
|
|
+
|
|
+ if (ch_idx == 0) {
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
|
|
+ } else {
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
|
|
+ }
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0x05);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, 0x00);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0x01);
|
|
+ if (ch_idx == 0)
|
|
+ rt2800_bbp_write(rt2x00dev, 159, 0x00);
|
|
+ else
|
|
+ rt2800_bbp_write(rt2x00dev, 159, 0x01);
|
|
+
|
|
+ vga_gain[ch_idx] = 18;
|
|
+ for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
|
|
+ rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]);
|
|
+ rt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]);
|
|
+
|
|
+ macvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3);
|
|
+ macvalue &= (~0x0000F1F1);
|
|
+ macvalue |= (rf_gain[rf_alc_idx] << 4);
|
|
+ macvalue |= (rf_gain[rf_alc_idx] << 12);
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue);
|
|
+ macvalue = (0x0000F1F1);
|
|
+ rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue);
|
|
+
|
|
+ if (rf_alc_idx == 0) {
|
|
+ rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21);
|
|
+ for (;vga_gain[ch_idx] > 0;vga_gain[ch_idx] = vga_gain[ch_idx] - 2) {
|
|
+ rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
|
|
+ rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
|
|
+ rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
|
|
+ rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
|
|
+ rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
|
|
+ p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
|
|
+ rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21);
|
|
+ p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
|
|
+ rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1);
|
|
+ if ((p0 < 7000*7000) && (p1 < (7000*7000))) {
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
|
|
+ rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
|
|
+
|
|
+ rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n",vga_gain[ch_idx], rfvga_gain_table[vga_gain[ch_idx]]);
|
|
+
|
|
+ if (vga_gain[ch_idx] < 0)
|
|
+ vga_gain[ch_idx] = 0;
|
|
+ }
|
|
+
|
|
+ rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
|
|
+
|
|
+ rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
|
|
+ rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
|
|
+
|
|
+ rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result);
|
|
+ }
|
|
+ }
|
|
+
|
|
+ for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
|
|
+ for (idx = 0; idx < 4; idx++) {
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0xB0);
|
|
+ bbp = (idx<<2) + rf_alc_idx;
|
|
+ rt2800_bbp_write(rt2x00dev, 159, bbp);
|
|
+ rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0xb1);
|
|
+ bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00];
|
|
+ bbp = bbp & 0x3F;
|
|
+ rt2800_bbp_write(rt2x00dev, 159, bbp);
|
|
+ rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0xb2);
|
|
+ bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01];
|
|
+ bbp = bbp & 0x3F;
|
|
+ rt2800_bbp_write(rt2x00dev, 159, bbp);
|
|
+ rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0xb8);
|
|
+ bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00];
|
|
+ bbp = bbp & 0x3F;
|
|
+ rt2800_bbp_write(rt2x00dev, 159, bbp);
|
|
+ rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0xb9);
|
|
+ bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01];
|
|
+ bbp = bbp & 0x3F;
|
|
+ rt2800_bbp_write(rt2x00dev, 159, bbp);
|
|
+ rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp);
|
|
+ }
|
|
+ }
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 23, 0x00);
|
|
+ rt2800_bbp_write(rt2x00dev, 24, 0x00);
|
|
+
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0x00);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, 0x00);
|
|
+
|
|
+ bbp = 0x00;
|
|
+ rt2800_bbp_write(rt2x00dev, 244, 0x00);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 21, 0x01);
|
|
+ udelay(1);
|
|
+ rt2800_bbp_write(rt2x00dev, 21, 0x00);
|
|
+
|
|
+ rt2800_rf_configrecover(rt2x00dev, rf_store);
|
|
+
|
|
+ rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
|
|
+ rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
|
|
+ udelay(1);
|
|
+ rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
|
|
+ rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
|
|
+ rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL2, orig528);
|
|
+ rt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c);
|
|
+ rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
|
|
+
|
|
+ rt2x00_info(rt2x00dev, "LOFT Calibration Done!\n");
|
|
+
|
|
+ savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
|
|
+ macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
|
|
+ macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
|
|
+ macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
|
|
+ macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
|
|
+ macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
|
|
+
|
|
+ bbpr1 = rt2800_bbp_read(rt2x00dev, 1);
|
|
+ bbpr4 = rt2800_bbp_read(rt2x00dev, 4);
|
|
+ bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
|
|
+ bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
|
|
+ mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
|
|
+
|
|
+ macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
|
|
+ macvalue &= (~0x04);
|
|
+ rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
|
|
+ for (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {
|
|
+ macvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
|
|
+ if (macvalue & 0x01)
|
|
+ udelay(50);
|
|
+ else
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
|
|
+ macvalue &= (~0x08);
|
|
+ rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
|
|
+ for (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {
|
|
+ macvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
|
|
+ if (macvalue & 0x02)
|
|
+ udelay(50);
|
|
+ else
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101);
|
|
+ rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
|
|
+ }
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 23, 0x00);
|
|
+ rt2800_bbp_write(rt2x00dev, 24, 0x00);
|
|
+
|
|
+ if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
|
|
+ rt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18));
|
|
+ rt2800_bbp_write(rt2x00dev, 21, 0x01);
|
|
+ udelay(1);
|
|
+ rt2800_bbp_write(rt2x00dev, 21, 0x00);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 241, 0x14);
|
|
+ rt2800_bbp_write(rt2x00dev, 242, 0x80);
|
|
+ rt2800_bbp_write(rt2x00dev, 244, 0x31);
|
|
+ } else {
|
|
+ rt2800_setbbptonegenerator(rt2x00dev);
|
|
+ }
|
|
+
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
|
|
+ rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
|
|
+ udelay(1);
|
|
+
|
|
+ rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
|
|
+
|
|
+ if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000);
|
|
+ rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
|
|
+ }
|
|
+
|
|
+ rt2800_register_write(rt2x00dev, 0x13b8, 0x00000010);
|
|
+
|
|
+ for (ch_idx = 0; ch_idx < 2; ch_idx++) {
|
|
+ rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
|
|
+ }
|
|
+
|
|
+ rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B);
|
|
+ rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0x03);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, 0x60);
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0xB0);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, 0x80);
|
|
+
|
|
+ for (ch_idx = 0; ch_idx < 2; ch_idx ++) {
|
|
+ rt2800_bbp_write(rt2x00dev, 23, 0x00);
|
|
+ rt2800_bbp_write(rt2x00dev, 24, 0x00);
|
|
+
|
|
+ if (ch_idx == 0) {
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0x01);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, 0x00);
|
|
+ if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
|
|
+ bbp = bbpr1 & (~0x18);
|
|
+ bbp = bbp | 0x00;
|
|
+ rt2800_bbp_write(rt2x00dev, 1, bbp);
|
|
+ }
|
|
+ rt2800_rf_aux_tx0_loopback(rt2x00dev);
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
|
|
+ } else {
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0x01);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, 0x01);
|
|
+ if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
|
|
+ bbp = bbpr1 & (~0x18);
|
|
+ bbp = bbp | 0x08;
|
|
+ rt2800_bbp_write(rt2x00dev, 1, bbp);
|
|
+ }
|
|
+ rt2800_rf_aux_tx1_loopback(rt2x00dev);
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
|
|
+ }
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0x05);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, 0x04);
|
|
+
|
|
+ bbp = (ch_idx == 0) ? 0x28 : 0x46;
|
|
+ rt2800_bbp_write(rt2x00dev, 158, bbp);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, 0x00);
|
|
+
|
|
+ if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
|
|
+ rt2800_bbp_write(rt2x00dev, 23, 0x06);
|
|
+ rt2800_bbp_write(rt2x00dev, 24, 0x06);
|
|
+ count_step = 1;
|
|
+ } else {
|
|
+ rt2800_bbp_write(rt2x00dev, 23, 0x1F);
|
|
+ rt2800_bbp_write(rt2x00dev, 24, 0x1F);
|
|
+ count_step = 2;
|
|
+ }
|
|
+
|
|
+ for (;vga_gain[ch_idx] < 19; vga_gain[ch_idx]=(vga_gain[ch_idx] + count_step)) {
|
|
+ rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
|
|
+ rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
|
|
+ rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
|
|
+
|
|
+ bbp = (ch_idx == 0) ? 0x29 : 0x47;
|
|
+ rt2800_bbp_write(rt2x00dev, 158, bbp);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, 0x00);
|
|
+ p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
|
|
+ if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
|
|
+ p0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
|
|
+ }
|
|
+
|
|
+ bbp = (ch_idx == 0) ? 0x29 : 0x47;
|
|
+ rt2800_bbp_write(rt2x00dev, 158, bbp);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, 0x21);
|
|
+ p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
|
|
+ if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
|
|
+ p1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
|
|
+ }
|
|
+
|
|
+ rt2x00_dbg(rt2x00dev, "IQ AGC %d %d\n", p0, p1);
|
|
+
|
|
+ if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
|
|
+ rt2x00_dbg(rt2x00dev, "IQ AGC IDX 10 %d %d\n", p0_idx10, p1_idx10);
|
|
+ if ((p0_idx10 > 7000*7000) || (p1_idx10 > 7000*7000)) {
|
|
+ if (vga_gain[ch_idx]!=0)
|
|
+ vga_gain[ch_idx] = vga_gain[ch_idx]-1;
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if ((p0 > 2500*2500) || (p1 > 2500*2500)) {
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (vga_gain[ch_idx] > 18)
|
|
+ vga_gain[ch_idx] = 18;
|
|
+ rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n",vga_gain[ch_idx], rfvga_gain_table[vga_gain[ch_idx]]);
|
|
+
|
|
+ bbp = (ch_idx == 0) ? 0x29 : 0x47;
|
|
+ rt2800_bbp_write(rt2x00dev, 158, bbp);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, 0x00);
|
|
+
|
|
+ rt2800_iq_search(rt2x00dev, ch_idx, ger, per);
|
|
+ }
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 23, 0x00);
|
|
+ rt2800_bbp_write(rt2x00dev, 24, 0x00);
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0x28);
|
|
+ bbp = ger[CHAIN_0] & 0x0F;
|
|
+ rt2800_bbp_write(rt2x00dev, 159, bbp);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0x29);
|
|
+ bbp = per[CHAIN_0] & 0x3F;
|
|
+ rt2800_bbp_write(rt2x00dev, 159, bbp);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0x46);
|
|
+ bbp = ger[CHAIN_1] & 0x0F;
|
|
+ rt2800_bbp_write(rt2x00dev, 159, bbp);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0x47);
|
|
+ bbp = per[CHAIN_1] & 0x3F;
|
|
+ rt2800_bbp_write(rt2x00dev, 159, bbp);
|
|
+
|
|
+ if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
|
|
+ rt2800_bbp_write(rt2x00dev, 1, bbpr1);
|
|
+ rt2800_bbp_write(rt2x00dev, 241, bbpr241);
|
|
+ rt2800_bbp_write(rt2x00dev, 242, bbpr242);
|
|
+ }
|
|
+ rt2800_bbp_write(rt2x00dev, 244, 0x00);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0x00);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, 0x00);
|
|
+ rt2800_bbp_write(rt2x00dev, 158, 0xB0);
|
|
+ rt2800_bbp_write(rt2x00dev, 159, 0x00);
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 30, bbpr30);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39);
|
|
+ rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
|
|
+
|
|
+ if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
|
|
+ rt2800_bbp_write(rt2x00dev, 4, bbpr4);
|
|
+ }
|
|
+
|
|
+ rt2800_bbp_write(rt2x00dev, 21, 0x01);
|
|
+ udelay(1);
|
|
+ rt2800_bbp_write(rt2x00dev, 21, 0x00);
|
|
+
|
|
+ rt2800_rf_configrecover(rt2x00dev, rf_store);
|
|
+
|
|
+ rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
|
|
+ rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
|
|
+ udelay(1);
|
|
+ rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
|
|
+ rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
|
|
+ rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
|
|
+ rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
|
|
+ rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
|
|
+
|
|
+ rt2x00_info(rt2x00dev, "TX IQ Calibration Done!\n");
|
|
+
|
|
+ return;
|
|
+}
|
|
+
|
|
static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
|
|
bool set_bw, bool is_ht40)
|
|
{
|
|
@@ -9675,6 +10612,7 @@ static void rt2800_init_rfcsr_6352(struc
|
|
rt2800_rxdcoc_calibration(rt2x00dev);
|
|
rt2800_bw_filter_calibration(rt2x00dev, true);
|
|
rt2800_bw_filter_calibration(rt2x00dev, false);
|
|
+ rt2800_loft_iq_calibration(rt2x00dev);
|
|
rt2800_rxiq_calibration(rt2x00dev);
|
|
}
|
|
|
|
--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
|
|
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
|
|
@@ -17,6 +17,16 @@
|
|
#define WCID_START 33
|
|
#define WCID_END 222
|
|
#define STA_IDS_SIZE (WCID_END - WCID_START + 2)
|
|
+#define CHAIN_0 0x0
|
|
+#define CHAIN_1 0x1
|
|
+#define RF_ALC_NUM 6
|
|
+#define CHAIN_NUM 2
|
|
+
|
|
+typedef struct rf_reg_pair {
|
|
+ u8 bank;
|
|
+ u8 reg;
|
|
+ u8 value;
|
|
+} rf_reg_pair;
|
|
|
|
/* RT2800 driver data structure */
|
|
struct rt2800_drv_data {
|