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437 lines
12 KiB
Diff
437 lines
12 KiB
Diff
--- a/arch/mips/pci/Makefile
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+++ b/arch/mips/pci/Makefile
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@@ -55,6 +55,7 @@ obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capc
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obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
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obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
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obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
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+obj-$(CONFIG_LANTIQ) += pci-lantiq.o ops-lantiq.o
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ifdef CONFIG_PCI_MSI
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obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
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--- /dev/null
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+++ b/arch/mips/pci/ops-lantiq.c
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@@ -0,0 +1,127 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/types.h>
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+#include <linux/pci.h>
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/delay.h>
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+#include <linux/mm.h>
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+#include <asm/addrspace.h>
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+#include <linux/vmalloc.h>
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+
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+#include <xway.h>
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+
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+#define LQ_PCI_CFG_BUSNUM_SHF 16
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+#define LQ_PCI_CFG_DEVNUM_SHF 11
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+#define LQ_PCI_CFG_FUNNUM_SHF 8
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+
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+#define PCI_ACCESS_READ 0
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+#define PCI_ACCESS_WRITE 1
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+
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+extern u32 lq_pci_mapped_cfg;
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+
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+static int
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+lq_pci_config_access(unsigned char access_type,
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+ struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
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+{
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+ unsigned long cfg_base;
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+ unsigned long flags;
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+
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+ u32 temp;
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+
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+ /* we support slot from 0 to 15 */
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+ /* dev_fn 0&0x68 (AD29) is ifxmips itself */
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+ if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
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+ || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
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+ return 1;
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+
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+ spin_lock_irqsave(&ebu_lock, flags);
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+
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+ cfg_base = lq_pci_mapped_cfg;
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+ cfg_base |= (bus->number << LQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
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+ LQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
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+
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+ /* Perform access */
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+ if (access_type == PCI_ACCESS_WRITE)
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+ {
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+#ifdef CONFIG_SWAP_IO_SPACE
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+ lq_w32(swab32(*data), ((u32*)cfg_base));
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+#else
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+ lq_w32(*data, ((u32*)cfg_base));
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+#endif
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+ } else {
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+ *data = lq_r32(((u32*)(cfg_base)));
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+#ifdef CONFIG_SWAP_IO_SPACE
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+ *data = swab32(*data);
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+#endif
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+ }
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+ wmb();
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+
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+ /* clean possible Master abort */
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+ cfg_base = (lq_pci_mapped_cfg | (0x0 << LQ_PCI_CFG_FUNNUM_SHF)) + 4;
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+ temp = lq_r32(((u32*)(cfg_base)));
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+#ifdef CONFIG_SWAP_IO_SPACE
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+ temp = swab32 (temp);
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+#endif
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+ cfg_base = (lq_pci_mapped_cfg | (0x68 << LQ_PCI_CFG_FUNNUM_SHF)) + 4;
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+ lq_w32(temp, ((u32*)cfg_base));
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+
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+ spin_unlock_irqrestore(&ebu_lock, flags);
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+
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+ if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
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+ return 1;
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+
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+ return 0;
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+}
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+
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+int
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+lq_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 * val)
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+{
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+ u32 data = 0;
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+
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+ if (lq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ if (size == 1)
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+ *val = (data >> ((where & 3) << 3)) & 0xff;
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+ else if (size == 2)
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+ *val = (data >> ((where & 3) << 3)) & 0xffff;
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+ else
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+ *val = data;
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+
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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+int
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+lq_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 val)
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+{
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+ u32 data = 0;
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+
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+ if (size == 4)
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+ {
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+ data = val;
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+ } else {
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+ if (lq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ if (size == 1)
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+ data = (data & ~(0xff << ((where & 3) << 3))) |
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+ (val << ((where & 3) << 3));
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+ else if (size == 2)
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+ data = (data & ~(0xffff << ((where & 3) << 3))) |
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+ (val << ((where & 3) << 3));
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+ }
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+
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+ if (lq_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ return PCIBIOS_SUCCESSFUL;
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+}
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--- /dev/null
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+++ b/arch/mips/pci/pci-lantiq.c
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@@ -0,0 +1,293 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/types.h>
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+#include <linux/pci.h>
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/delay.h>
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+#include <linux/mm.h>
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+#include <linux/vmalloc.h>
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+#include <linux/platform_device.h>
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+
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+#include <asm/gpio.h>
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+#include <asm/addrspace.h>
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+
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+#include <xway.h>
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+#include <xway_irq.h>
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+#include <lantiq_platform.h>
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+
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+#define LQ_PCI_CFG_BASE 0x17000000
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+#define LQ_PCI_CFG_SIZE 0x00008000
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+#define LQ_PCI_MEM_BASE 0x18000000
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+#define LQ_PCI_MEM_SIZE 0x02000000
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+#define LQ_PCI_IO_BASE 0x1AE00000
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+#define LQ_PCI_IO_SIZE 0x00200000
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+
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+#define PCI_CR_FCI_ADDR_MAP0 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C0))
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+#define PCI_CR_FCI_ADDR_MAP1 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C4))
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+#define PCI_CR_FCI_ADDR_MAP2 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C8))
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+#define PCI_CR_FCI_ADDR_MAP3 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00CC))
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+#define PCI_CR_FCI_ADDR_MAP4 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D0))
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+#define PCI_CR_FCI_ADDR_MAP5 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D4))
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+#define PCI_CR_FCI_ADDR_MAP6 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D8))
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+#define PCI_CR_FCI_ADDR_MAP7 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00DC))
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+#define PCI_CR_CLK_CTRL ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0000))
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+#define PCI_CR_PCI_MOD ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0030))
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+#define PCI_CR_PC_ARB ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0080))
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+#define PCI_CR_FCI_ADDR_MAP11hg ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E4))
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+#define PCI_CR_BAR11MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0044))
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+#define PCI_CR_BAR12MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0048))
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+#define PCI_CR_BAR13MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x004C))
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+#define PCI_CS_BASE_ADDR1 ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0010))
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+#define PCI_CR_PCI_ADDR_MAP11 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0064))
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+#define PCI_CR_FCI_BURST_LENGTH ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E8))
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+#define PCI_CR_PCI_EOI ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x002C))
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+
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+
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+#define PCI_CS_STS_CMD ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0004))
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+
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+#define PCI_MASTER0_REQ_MASK_2BITS 8
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+#define PCI_MASTER1_REQ_MASK_2BITS 10
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+#define PCI_MASTER2_REQ_MASK_2BITS 12
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+#define INTERNAL_ARB_ENABLE_BIT 0
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+
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+#define LQ_CGU_IFCCR ((u32 *)(LQ_CGU_BASE_ADDR + 0x0018))
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+#define LQ_CGU_PCICR ((u32 *)(LQ_CGU_BASE_ADDR + 0x0034))
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+
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+extern int lq_pci_read_config_dword(struct pci_bus *bus,
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+ unsigned int devfn, int where, int size, u32 *val);
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+extern int lq_pci_write_config_dword(struct pci_bus *bus,
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+ unsigned int devfn, int where, int size, u32 val);
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+
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+u32 lq_pci_mapped_cfg;
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+
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+/* Since the PCI REQ pins can be reused for other functionality, make it possible
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+ to exclude those from interpretation by the PCI controller */
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+static int lq_pci_req_mask = 0xf;
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+
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+struct pci_ops lq_pci_ops =
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+{
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+ .read = lq_pci_read_config_dword,
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+ .write = lq_pci_write_config_dword
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+};
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+
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+static struct resource pci_io_resource =
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+{
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+ .name = "pci io space",
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+ .start = LQ_PCI_IO_BASE,
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+ .end = LQ_PCI_IO_BASE + LQ_PCI_IO_SIZE - 1,
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+ .flags = IORESOURCE_IO
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+};
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+
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+static struct resource pci_mem_resource =
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+{
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+ .name = "pci memory space",
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+ .start = LQ_PCI_MEM_BASE,
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+ .end = LQ_PCI_MEM_BASE + LQ_PCI_MEM_SIZE - 1,
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+ .flags = IORESOURCE_MEM
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+};
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+
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+static struct pci_controller lq_pci_controller =
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+{
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+ .pci_ops = &lq_pci_ops,
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+ .mem_resource = &pci_mem_resource,
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+ .mem_offset = 0x00000000UL,
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+ .io_resource = &pci_io_resource,
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+ .io_offset = 0x00000000UL,
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+};
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+
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+int
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+pcibios_plat_dev_init(struct pci_dev *dev)
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+{
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+ u8 pin;
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+
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+ pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
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+ switch(pin)
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+ {
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+ case 0:
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+ break;
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+ case 1:
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+ //falling edge level triggered:0x4, low level:0xc, rising edge:0x2
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+ lq_w32(lq_r32(LQ_EBU_PCC_CON) | 0xc, LQ_EBU_PCC_CON);
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+ lq_w32(lq_r32(LQ_EBU_PCC_IEN) | 0x10, LQ_EBU_PCC_IEN);
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+ break;
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+ case 2:
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+ case 3:
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+ case 4:
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+ printk ("WARNING: interrupt pin %d not supported yet!\n", pin);
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+ default:
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+ printk ("WARNING: invalid interrupt pin %d\n", pin);
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+ return 1;
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+ }
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+ return 0;
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+}
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+
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+static u32
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+lq_calc_bar11mask(void)
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+{
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+ u32 mem, bar11mask;
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+
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+ /* BAR11MASK value depends on available memory on system. */
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+ mem = num_physpages * PAGE_SIZE;
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+ bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) -1)) -1)) | 8;
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+
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+ return bar11mask;
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+}
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+
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+static void
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+lq_pci_setup_clk(int external_clock)
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+{
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+ /* set clock to 33Mhz */
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+ lq_w32(lq_r32(LQ_CGU_IFCCR) & ~0xf00000, LQ_CGU_IFCCR);
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+ lq_w32(lq_r32(LQ_CGU_IFCCR) | 0x800000, LQ_CGU_IFCCR);
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+ if (external_clock)
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+ {
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+ lq_w32(lq_r32(LQ_CGU_IFCCR) & ~(1 << 16), LQ_CGU_IFCCR);
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+ lq_w32((1 << 30), LQ_CGU_PCICR);
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+ } else {
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+ lq_w32(lq_r32(LQ_CGU_IFCCR) | (1 << 16), LQ_CGU_IFCCR);
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+ lq_w32((1 << 31) | (1 << 30), LQ_CGU_PCICR);
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+ }
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+}
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+
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+static void
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+lq_pci_setup_gpio(void)
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+{
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+ /* PCI reset line is gpio driven */
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+ lq_gpio_request(21, 0, 0, 1, "pci-reset");
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+
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+ /* PCI_REQ line */
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+ lq_gpio_request(29, 1, 0, 0, "pci-req");
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+
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+ /* PCI_GNT line */
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+ lq_gpio_request(30, 1, 0, 1, "pci-gnt");
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+}
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+
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+static int __init
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+lq_pci_startup(void)
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+{
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+ u32 temp_buffer;
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+
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+ /* setup pci clock and gpis used by pci */
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+ lq_pci_setup_gpio();
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+
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+ /* enable auto-switching between PCI and EBU */
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+ lq_w32(0xa, PCI_CR_CLK_CTRL);
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+
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+ /* busy, i.e. configuration is not done, PCI access has to be retried */
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+ lq_w32(lq_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
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+ wmb ();
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+ /* BUS Master/IO/MEM access */
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+ lq_w32(lq_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
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+
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+ /* enable external 2 PCI masters */
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+ temp_buffer = lq_r32(PCI_CR_PC_ARB);
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+ temp_buffer &= (~(lq_pci_req_mask << 16));
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+ /* enable internal arbiter */
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+ temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
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+ /* enable internal PCI master reqest */
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+ temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
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+
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+ /* enable EBU request */
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+ temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
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+
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+ /* enable all external masters request */
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+ temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
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+ lq_w32(temp_buffer, PCI_CR_PC_ARB);
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+ wmb ();
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+
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+ /* setup BAR memory regions */
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+ lq_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
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+ lq_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
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+ lq_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
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+ lq_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
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+ lq_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
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+ lq_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
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+ lq_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
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+ lq_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
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+ lq_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
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+ lq_w32(lq_calc_bar11mask(), PCI_CR_BAR11MASK);
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+ lq_w32(0, PCI_CR_PCI_ADDR_MAP11);
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+ lq_w32(0, PCI_CS_BASE_ADDR1);
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+#ifdef CONFIG_SWAP_IO_SPACE
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+ /* both TX and RX endian swap are enabled */
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+ lq_w32(lq_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
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+ wmb ();
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+#endif
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+ /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
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+ lq_w32(lq_r32(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
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+ lq_w32(lq_r32(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
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+ /*use 8 dw burst length */
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+ lq_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
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+ lq_w32(lq_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
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+ wmb();
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+
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+ /* toggle reset pin */
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+ __gpio_set_value(21, 0);
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+ wmb();
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+ mdelay(1);
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+ __gpio_set_value(21, 1);
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+ return 0;
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+}
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+
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+int __init
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+pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
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+ switch(slot)
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+ {
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+ case 13:
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+ /* IDSEL = AD29 --> USB Host Controller */
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+ return (INT_NUM_IM1_IRL0 + 17);
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+ case 14:
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+ /* IDSEL = AD30 --> mini PCI connector */
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+ return (INT_NUM_IM0_IRL0 + 22);
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+ default:
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+ printk("lq_pci: no IRQ found for slot %d, pin %d\n", slot, pin);
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+ return 0;
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+ }
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+}
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+
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+static int
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+lq_pci_probe(struct platform_device *pdev)
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+{
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+ struct lq_pci_data *lq_pci_data = (struct lq_pci_data*) pdev->dev.platform_data;
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+ extern int pci_probe_only;
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+
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+ pci_probe_only = 0;
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+ lq_pci_req_mask = lq_pci_data->req_mask;
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+ lq_pci_setup_clk(lq_pci_data->clock);
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+
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+ lq_pci_startup();
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+ lq_pci_mapped_cfg =
|
|
+ (u32)ioremap_nocache(LQ_PCI_CFG_BASE, LQ_PCI_CFG_BASE);
|
|
+ lq_pci_controller.io_map_base =
|
|
+ (unsigned long)ioremap(LQ_PCI_IO_BASE, LQ_PCI_IO_SIZE - 1);
|
|
+
|
|
+ register_pci_controller(&lq_pci_controller);
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static struct platform_driver
|
|
+lq_pci_driver = {
|
|
+ .probe = lq_pci_probe,
|
|
+ .driver = {
|
|
+ .name = "lq_pci",
|
|
+ .owner = THIS_MODULE,
|
|
+ },
|
|
+};
|
|
+
|
|
+int __init
|
|
+pcibios_init(void)
|
|
+{
|
|
+ int ret = platform_driver_register(&lq_pci_driver);
|
|
+ if(ret)
|
|
+ printk(KERN_INFO "lq_pci: Error registering platfom driver!");
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+arch_initcall(pcibios_init);
|