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201 lines
6.9 KiB
Diff
201 lines
6.9 KiB
Diff
From ef00ad56d728618203358d9eba7ca8e7eb48e701 Mon Sep 17 00:00:00 2001
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From: Matthew McClintock <mmcclint@codeaurora.org>
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Date: Tue, 26 Apr 2016 12:57:46 -0500
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Subject: [PATCH 12/37] spi: qup: refactor spi_qup_io_config in two functions
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This is preparation for handling transactions larger than 64K-1 bytes in
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block mode which is currently unsupported quietly fails.
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We need to break these into two functions 1) prep is called once per
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spi_message and 2) io_config is calle once per spi-qup bus transaction
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This is just refactoring, there should be no functional change
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Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
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---
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drivers/spi/spi-qup.c | 141 ++++++++++++++++++++++++++++++-------------------
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1 file changed, 86 insertions(+), 55 deletions(-)
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--- a/drivers/spi/spi-qup.c
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+++ b/drivers/spi/spi-qup.c
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@@ -585,12 +585,11 @@ static irqreturn_t spi_qup_qup_irq(int i
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return IRQ_HANDLED;
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}
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-/* set clock freq ... bits per word */
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-static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
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+/* set clock freq ... bits per word, determine mode */
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+static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer)
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{
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struct spi_qup *controller = spi_master_get_devdata(spi->master);
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- u32 config, iomode, control;
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- int ret, n_words;
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+ int ret;
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if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
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dev_err(controller->dev, "too big size for loopback %d > %d\n",
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@@ -605,56 +604,94 @@ static int spi_qup_io_config(struct spi_
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return -EIO;
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}
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- if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
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- dev_err(controller->dev, "cannot set RESET state\n");
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- return -EIO;
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- }
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-
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controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8);
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controller->n_words = xfer->len / controller->w_size;
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- n_words = controller->n_words;
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- if (n_words <= (controller->in_fifo_sz / sizeof(u32))) {
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+ if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32)))
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controller->mode = QUP_IO_M_MODE_FIFO;
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- writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
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- writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT);
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- /* must be zero for FIFO */
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- writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
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- writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
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- } else if (spi->master->can_dma &&
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- spi->master->can_dma(spi->master, spi, xfer) &&
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- spi->master->cur_msg_mapped) {
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+ else if (spi->master->can_dma &&
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+ spi->master->can_dma(spi->master, spi, xfer) &&
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+ spi->master->cur_msg_mapped)
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controller->mode = QUP_IO_M_MODE_BAM;
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- writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
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- writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
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- /* must be zero for BLOCK and BAM */
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- writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
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- writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
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+ else
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+ controller->mode = QUP_IO_M_MODE_BLOCK;
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- if (!controller->qup_v1) {
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- void __iomem *input_cnt;
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+ return 0;
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+}
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- input_cnt = controller->base + QUP_MX_INPUT_CNT;
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- /*
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- * for DMA transfers, both QUP_MX_INPUT_CNT and
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- * QUP_MX_OUTPUT_CNT must be zero to all cases but one.
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- * That case is a non-balanced transfer when there is
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- * only a rx_buf.
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- */
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- if (xfer->tx_buf)
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- writel_relaxed(0, input_cnt);
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- else
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- writel_relaxed(n_words, input_cnt);
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+/* prep qup for another spi transaction of specific type */
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+static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
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+{
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+ struct spi_qup *controller = spi_master_get_devdata(spi->master);
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+ u32 config, iomode, control;
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+ unsigned long flags;
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+ reinit_completion(&controller->done);
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+ reinit_completion(&controller->dma_tx_done);
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+
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+ spin_lock_irqsave(&controller->lock, flags);
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+ controller->xfer = xfer;
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+ controller->error = 0;
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+ controller->rx_bytes = 0;
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+ controller->tx_bytes = 0;
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+ spin_unlock_irqrestore(&controller->lock, flags);
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+
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+
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+ if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
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+ dev_err(controller->dev, "cannot set RESET state\n");
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+ return -EIO;
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+ }
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+
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+ switch (controller->mode) {
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+ case QUP_IO_M_MODE_FIFO:
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+ writel_relaxed(controller->n_words,
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+ controller->base + QUP_MX_READ_CNT);
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+ writel_relaxed(controller->n_words,
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+ controller->base + QUP_MX_WRITE_CNT);
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+ /* must be zero for FIFO */
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+ writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
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writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
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- }
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- } else {
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- controller->mode = QUP_IO_M_MODE_BLOCK;
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- writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
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- writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
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- /* must be zero for BLOCK and BAM */
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- writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
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- writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
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+ break;
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+ case QUP_IO_M_MODE_BAM:
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+ writel_relaxed(controller->n_words,
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+ controller->base + QUP_MX_INPUT_CNT);
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+ writel_relaxed(controller->n_words,
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+ controller->base + QUP_MX_OUTPUT_CNT);
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+ /* must be zero for BLOCK and BAM */
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+ writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
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+ writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
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+ if (!controller->qup_v1) {
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+ void __iomem *input_cnt;
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+
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+ input_cnt = controller->base + QUP_MX_INPUT_CNT;
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+ /*
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+ * for DMA transfers, both QUP_MX_INPUT_CNT and
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+ * QUP_MX_OUTPUT_CNT must be zero to all cases
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+ * but one. That case is a non-balanced
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+ * transfer when there is only a rx_buf.
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+ */
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+ if (xfer->tx_buf)
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+ writel_relaxed(0, input_cnt);
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+ else
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+ writel_relaxed(controller->n_words,
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+ input_cnt);
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+
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+ writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
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+ }
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+ break;
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+ case QUP_IO_M_MODE_BLOCK:
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+ writel_relaxed(controller->n_words,
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+ controller->base + QUP_MX_INPUT_CNT);
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+ writel_relaxed(controller->n_words,
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+ controller->base + QUP_MX_OUTPUT_CNT);
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+ /* must be zero for BLOCK and BAM */
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+ writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
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+ writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
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+ break;
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+ default:
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+ dev_err(controller->dev, "unknown mode = %d\n",
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+ controller->mode);
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+ return -EIO;
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}
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iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
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@@ -743,6 +780,10 @@ static int spi_qup_transfer_one(struct s
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unsigned long timeout, flags;
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int ret = -EIO;
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+ ret = spi_qup_io_prep(spi, xfer);
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+ if (ret)
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+ return ret;
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+
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ret = spi_qup_io_config(spi, xfer);
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if (ret)
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return ret;
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@@ -751,16 +792,6 @@ static int spi_qup_transfer_one(struct s
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timeout = DIV_ROUND_UP(xfer->len * 8, timeout);
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timeout = 100 * msecs_to_jiffies(timeout);
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- reinit_completion(&controller->done);
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- reinit_completion(&controller->dma_tx_done);
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-
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- spin_lock_irqsave(&controller->lock, flags);
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- controller->xfer = xfer;
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- controller->error = 0;
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- controller->rx_bytes = 0;
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- controller->tx_bytes = 0;
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- spin_unlock_irqrestore(&controller->lock, flags);
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-
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if (spi_qup_is_dma_xfer(controller->mode))
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ret = spi_qup_do_dma(master, xfer, timeout);
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else
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