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311 lines
9.2 KiB
Diff
311 lines
9.2 KiB
Diff
From 4dc7631bbf7c7ac7548026ce45d889235e4f5892 Mon Sep 17 00:00:00 2001
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From: Andy Gross <andy.gross@linaro.org>
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Date: Sun, 31 Jan 2016 21:28:13 -0600
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Subject: [PATCH 09/37] spi: qup: Fix block mode to work correctly
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This patch corrects the behavior of the BLOCK transactions. During block
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transactions, the controller must be read/written to in block size transactions.
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Signed-off-by: Andy Gross <andy.gross@linaro.org>
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---
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drivers/spi/spi-qup.c | 182 ++++++++++++++++++++++++++++++++++++++-----------
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1 file changed, 142 insertions(+), 40 deletions(-)
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--- a/drivers/spi/spi-qup.c
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+++ b/drivers/spi/spi-qup.c
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@@ -82,6 +82,8 @@
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#define QUP_IO_M_MODE_BAM 3
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/* QUP_OPERATIONAL fields */
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+#define QUP_OP_IN_BLOCK_READ_REQ BIT(13)
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+#define QUP_OP_OUT_BLOCK_WRITE_REQ BIT(12)
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#define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11)
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#define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10)
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#define QUP_OP_IN_SERVICE_FLAG BIT(9)
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@@ -155,6 +157,12 @@ struct spi_qup {
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struct dma_slave_config tx_conf;
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};
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+static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag)
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+{
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+ u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL);
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+
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+ return opflag & flag;
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+}
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static inline bool spi_qup_is_dma_xfer(int mode)
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{
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@@ -216,29 +224,26 @@ static int spi_qup_set_state(struct spi_
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return 0;
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}
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-static void spi_qup_fifo_read(struct spi_qup *controller,
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- struct spi_transfer *xfer)
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+static void spi_qup_read_from_fifo(struct spi_qup *controller,
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+ struct spi_transfer *xfer, u32 num_words)
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{
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u8 *rx_buf = xfer->rx_buf;
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- u32 word, state;
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- int idx, shift, w_size;
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-
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- w_size = controller->w_size;
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-
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- while (controller->rx_bytes < xfer->len) {
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+ int i, shift, num_bytes;
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+ u32 word;
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- state = readl_relaxed(controller->base + QUP_OPERATIONAL);
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- if (0 == (state & QUP_OP_IN_FIFO_NOT_EMPTY))
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- break;
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+ for (; num_words; num_words--) {
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word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
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+ num_bytes = min_t(int, xfer->len - controller->rx_bytes,
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+ controller->w_size);
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+
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if (!rx_buf) {
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- controller->rx_bytes += w_size;
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+ controller->rx_bytes += num_bytes;
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continue;
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}
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- for (idx = 0; idx < w_size; idx++, controller->rx_bytes++) {
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+ for (i = 0; i < num_bytes; i++, controller->rx_bytes++) {
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/*
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* The data format depends on bytes per SPI word:
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* 4 bytes: 0x12345678
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@@ -246,38 +251,80 @@ static void spi_qup_fifo_read(struct spi
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* 1 byte : 0x00000012
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*/
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shift = BITS_PER_BYTE;
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- shift *= (w_size - idx - 1);
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+ shift *= (controller->w_size - i - 1);
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rx_buf[controller->rx_bytes] = word >> shift;
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}
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}
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}
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-static void spi_qup_fifo_write(struct spi_qup *controller,
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+static void spi_qup_read(struct spi_qup *controller,
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struct spi_transfer *xfer)
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{
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- const u8 *tx_buf = xfer->tx_buf;
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- u32 word, state, data;
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- int idx, w_size;
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+ u32 remainder, words_per_block, num_words;
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+ bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
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- w_size = controller->w_size;
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+ remainder = DIV_ROUND_UP(xfer->len - controller->rx_bytes,
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+ controller->w_size);
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+ words_per_block = controller->in_blk_sz >> 2;
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- while (controller->tx_bytes < xfer->len) {
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+ do {
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+ /* ACK by clearing service flag */
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+ writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
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+ controller->base + QUP_OPERATIONAL);
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- state = readl_relaxed(controller->base + QUP_OPERATIONAL);
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- if (state & QUP_OP_OUT_FIFO_FULL)
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+ if (is_block_mode) {
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+ num_words = (remainder > words_per_block) ?
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+ words_per_block : remainder;
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+ } else {
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+ if (!spi_qup_is_flag_set(controller,
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+ QUP_OP_IN_FIFO_NOT_EMPTY))
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+ break;
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+
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+ num_words = 1;
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+ }
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+
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+ /* read up to the maximum transfer size available */
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+ spi_qup_read_from_fifo(controller, xfer, num_words);
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+
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+ remainder -= num_words;
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+
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+ /* if block mode, check to see if next block is available */
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+ if (is_block_mode && !spi_qup_is_flag_set(controller,
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+ QUP_OP_IN_BLOCK_READ_REQ))
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break;
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+ } while (remainder);
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+
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+ /*
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+ * Due to extra stickiness of the QUP_OP_IN_SERVICE_FLAG during block
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+ * mode reads, it has to be cleared again at the very end
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+ */
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+ if (is_block_mode && spi_qup_is_flag_set(controller,
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+ QUP_OP_MAX_INPUT_DONE_FLAG))
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+ writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
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+ controller->base + QUP_OPERATIONAL);
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+
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+}
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+
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+static void spi_qup_write_to_fifo(struct spi_qup *controller,
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+ struct spi_transfer *xfer, u32 num_words)
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+{
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+ const u8 *tx_buf = xfer->tx_buf;
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+ int i, num_bytes;
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+ u32 word, data;
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+
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+ for (; num_words; num_words--) {
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word = 0;
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- for (idx = 0; idx < w_size; idx++, controller->tx_bytes++) {
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- if (!tx_buf) {
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- controller->tx_bytes += w_size;
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- break;
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+ num_bytes = min_t(int, xfer->len - controller->tx_bytes,
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+ controller->w_size);
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+ if (tx_buf)
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+ for (i = 0; i < num_bytes; i++) {
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+ data = tx_buf[controller->tx_bytes + i];
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+ word |= data << (BITS_PER_BYTE * (3 - i));
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}
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- data = tx_buf[controller->tx_bytes];
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- word |= data << (BITS_PER_BYTE * (3 - idx));
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- }
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+ controller->tx_bytes += num_bytes;
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writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
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}
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@@ -290,6 +337,44 @@ static void spi_qup_dma_done(void *data)
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complete(done);
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}
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+static void spi_qup_write(struct spi_qup *controller,
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+ struct spi_transfer *xfer)
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+{
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+ bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
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+ u32 remainder, words_per_block, num_words;
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+
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+ remainder = DIV_ROUND_UP(xfer->len - controller->tx_bytes,
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+ controller->w_size);
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+ words_per_block = controller->out_blk_sz >> 2;
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+
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+ do {
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+ /* ACK by clearing service flag */
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+ writel_relaxed(QUP_OP_OUT_SERVICE_FLAG,
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+ controller->base + QUP_OPERATIONAL);
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+
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+ if (is_block_mode) {
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+ num_words = (remainder > words_per_block) ?
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+ words_per_block : remainder;
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+ } else {
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+ if (spi_qup_is_flag_set(controller,
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+ QUP_OP_OUT_FIFO_FULL))
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+ break;
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+
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+ num_words = 1;
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+ }
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+
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+ spi_qup_write_to_fifo(controller, xfer, num_words);
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+
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+ remainder -= num_words;
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+
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+ /* if block mode, check to see if next block is available */
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+ if (is_block_mode && !spi_qup_is_flag_set(controller,
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+ QUP_OP_OUT_BLOCK_WRITE_REQ))
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+ break;
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+
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+ } while (remainder);
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+}
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+
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static int spi_qup_prep_sg(struct spi_master *master, struct spi_transfer *xfer,
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enum dma_transfer_direction dir,
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dma_async_tx_callback callback,
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@@ -347,11 +432,13 @@ unsigned long timeout)
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return ret;
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}
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- if (xfer->rx_buf)
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- rx_done = spi_qup_dma_done;
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+ if (!qup->qup_v1) {
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+ if (xfer->rx_buf)
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+ rx_done = spi_qup_dma_done;
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- if (xfer->tx_buf)
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- tx_done = spi_qup_dma_done;
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+ if (xfer->tx_buf)
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+ tx_done = spi_qup_dma_done;
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+ }
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if (xfer->rx_buf) {
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ret = spi_qup_prep_sg(master, xfer, DMA_DEV_TO_MEM, rx_done,
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@@ -398,7 +485,8 @@ static int spi_qup_do_pio(struct spi_mas
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return ret;
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}
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- spi_qup_fifo_write(qup, xfer);
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+ if (qup->mode == QUP_IO_M_MODE_FIFO)
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+ spi_qup_write(qup, xfer);
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ret = spi_qup_set_state(qup, QUP_STATE_RUN);
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if (ret) {
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@@ -431,10 +519,11 @@ static irqreturn_t spi_qup_qup_irq(int i
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writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
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writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
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- writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
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if (!xfer) {
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- dev_err_ratelimited(controller->dev, "unexpected irq %08x %08x %08x\n",
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+ writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
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+ dev_err_ratelimited(controller->dev,
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+ "unexpected irq %08x %08x %08x\n",
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qup_err, spi_err, opflags);
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return IRQ_HANDLED;
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}
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@@ -460,12 +549,20 @@ static irqreturn_t spi_qup_qup_irq(int i
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error = -EIO;
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}
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- if (!spi_qup_is_dma_xfer(controller->mode)) {
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+ if (spi_qup_is_dma_xfer(controller->mode)) {
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+ writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
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+ if (opflags & QUP_OP_IN_SERVICE_FLAG &&
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+ opflags & QUP_OP_MAX_INPUT_DONE_FLAG)
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+ complete(&controller->done);
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+ if (opflags & QUP_OP_OUT_SERVICE_FLAG &&
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+ opflags & QUP_OP_MAX_OUTPUT_DONE_FLAG)
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+ complete(&controller->dma_tx_done);
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+ } else {
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if (opflags & QUP_OP_IN_SERVICE_FLAG)
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- spi_qup_fifo_read(controller, xfer);
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+ spi_qup_read(controller, xfer);
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if (opflags & QUP_OP_OUT_SERVICE_FLAG)
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- spi_qup_fifo_write(controller, xfer);
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+ spi_qup_write(controller, xfer);
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}
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spin_lock_irqsave(&controller->lock, flags);
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@@ -473,6 +570,9 @@ static irqreturn_t spi_qup_qup_irq(int i
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controller->xfer = xfer;
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spin_unlock_irqrestore(&controller->lock, flags);
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+ /* re-read opflags as flags may have changed due to actions above */
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+ opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
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+
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if ((controller->rx_bytes == xfer->len &&
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(opflags & QUP_OP_MAX_INPUT_DONE_FLAG)) || error)
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complete(&controller->done);
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@@ -516,11 +616,13 @@ static int spi_qup_io_config(struct spi_
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/* must be zero for FIFO */
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writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
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writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
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-
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} else if (spi->master->can_dma &&
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spi->master->can_dma(spi->master, spi, xfer) &&
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spi->master->cur_msg_mapped) {
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controller->mode = QUP_IO_M_MODE_BAM;
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+ writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
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+ writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
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+ /* must be zero for BLOCK and BAM */
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writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
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writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
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