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37 lines
1.2 KiB
Diff
37 lines
1.2 KiB
Diff
From 4422c4efeed2a8b9fa745c6e529623d89c0be75e Mon Sep 17 00:00:00 2001
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From: Chunfeng Yun <chunfeng.yun@mediatek.com>
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Date: Fri, 13 Oct 2017 16:26:35 +0800
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Subject: [PATCH 128/224] usb: xhci-mtk: check clock stability of U3_MAC
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This is useful to find out the root cause when the Super Speed doesn't
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work. Such as when the T-PHY is switched to PCIe or SATA, and affects
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Super Speed function, the check will fail.
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Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
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Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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drivers/usb/host/xhci-mtk.c | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/drivers/usb/host/xhci-mtk.c
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+++ b/drivers/usb/host/xhci-mtk.c
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@@ -43,6 +43,7 @@
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/* ip_pw_sts1 register */
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#define STS1_IP_SLEEP_STS BIT(30)
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+#define STS1_U3_MAC_RST BIT(16)
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#define STS1_XHCI_RST BIT(11)
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#define STS1_SYS125_RST BIT(10)
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#define STS1_REF_RST BIT(8)
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@@ -125,6 +126,9 @@ static int xhci_mtk_host_enable(struct x
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check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
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STS1_SYS125_RST | STS1_XHCI_RST;
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+ if (mtk->num_u3_ports)
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+ check_val |= STS1_U3_MAC_RST;
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+
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ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
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(check_val == (value & check_val)), 100, 20000);
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if (ret) {
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