You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
357 lines
12 KiB
Diff
357 lines
12 KiB
Diff
From 780865643e5dbf41fe950924a68f7ee4fea8af3e Mon Sep 17 00:00:00 2001
|
|
From: Biwen Li <biwen.li@nxp.com>
|
|
Date: Tue, 30 Oct 2018 18:26:39 +0800
|
|
Subject: [PATCH 30/40] ifc-nor-nand: support layerscape
|
|
This is an integrated patch of ifc-nor-nand for
|
|
layerscape
|
|
|
|
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
|
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
|
|
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
|
---
|
|
drivers/memory/fsl_ifc.c | 263 +++++++++++++++++++++++++++++
|
|
drivers/mtd/maps/physmap_of_core.c | 4 +
|
|
include/linux/fsl_ifc.h | 7 +
|
|
3 files changed, 274 insertions(+)
|
|
|
|
--- a/drivers/memory/fsl_ifc.c
|
|
+++ b/drivers/memory/fsl_ifc.c
|
|
@@ -24,6 +24,7 @@
|
|
#include <linux/compiler.h>
|
|
#include <linux/sched.h>
|
|
#include <linux/spinlock.h>
|
|
+#include <linux/delay.h>
|
|
#include <linux/types.h>
|
|
#include <linux/slab.h>
|
|
#include <linux/io.h>
|
|
@@ -37,6 +38,8 @@
|
|
|
|
struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
|
|
EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
|
|
+#define FSL_IFC_V1_3_0 0x01030000
|
|
+#define IFC_TIMEOUT_MSECS 1000 /* 1000ms */
|
|
|
|
/*
|
|
* convert_ifc_address - convert the base address
|
|
@@ -311,6 +314,261 @@ err:
|
|
return ret;
|
|
}
|
|
|
|
+#ifdef CONFIG_PM_SLEEP
|
|
+/* save ifc registers */
|
|
+static int fsl_ifc_suspend(struct device *dev)
|
|
+{
|
|
+ struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
|
|
+ struct fsl_ifc_global __iomem *fcm = ctrl->gregs;
|
|
+ struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
|
|
+ __be32 nand_evter_intr_en, cm_evter_intr_en, nor_evter_intr_en,
|
|
+ gpcm_evter_intr_en;
|
|
+ uint32_t ifc_bank, i;
|
|
+
|
|
+ ctrl->saved_gregs = kzalloc(sizeof(struct fsl_ifc_global), GFP_KERNEL);
|
|
+ if (!ctrl->saved_gregs)
|
|
+ return -ENOMEM;
|
|
+ ctrl->saved_rregs = kzalloc(sizeof(struct fsl_ifc_runtime), GFP_KERNEL);
|
|
+ if (!ctrl->saved_rregs)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ cm_evter_intr_en = ifc_in32(&fcm->cm_evter_intr_en);
|
|
+ nand_evter_intr_en = ifc_in32(&runtime->ifc_nand.nand_evter_intr_en);
|
|
+ nor_evter_intr_en = ifc_in32(&runtime->ifc_nor.nor_evter_intr_en);
|
|
+ gpcm_evter_intr_en = ifc_in32(&runtime->ifc_gpcm.gpcm_evter_intr_en);
|
|
+
|
|
+/* IFC interrupts disabled */
|
|
+
|
|
+ ifc_out32(0x0, &fcm->cm_evter_intr_en);
|
|
+ ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
|
|
+ ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
|
|
+ ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
|
|
+
|
|
+ if (ctrl->saved_gregs) {
|
|
+ for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
|
|
+ ctrl->saved_gregs->cspr_cs[ifc_bank].cspr_ext =
|
|
+ ifc_in32(&fcm->cspr_cs[ifc_bank].cspr_ext);
|
|
+ ctrl->saved_gregs->cspr_cs[ifc_bank].cspr =
|
|
+ ifc_in32(&fcm->cspr_cs[ifc_bank].cspr);
|
|
+ ctrl->saved_gregs->amask_cs[ifc_bank].amask =
|
|
+ ifc_in32(&fcm->amask_cs[ifc_bank].amask);
|
|
+ ctrl->saved_gregs->csor_cs[ifc_bank].csor_ext =
|
|
+ ifc_in32(&fcm->csor_cs[ifc_bank].csor_ext);
|
|
+ ctrl->saved_gregs->csor_cs[ifc_bank].csor =
|
|
+ ifc_in32(&fcm->csor_cs[ifc_bank].csor);
|
|
+ for (i = 0; i < 4; i++) {
|
|
+ ctrl->saved_gregs->ftim_cs[ifc_bank].ftim[i] =
|
|
+ ifc_in32(
|
|
+ &fcm->ftim_cs[ifc_bank].ftim[i]);
|
|
+ }
|
|
+ }
|
|
+
|
|
+ ctrl->saved_gregs->rb_map = ifc_in32(&fcm->rb_map);
|
|
+ ctrl->saved_gregs->wb_map = ifc_in32(&fcm->wb_map);
|
|
+ ctrl->saved_gregs->ifc_gcr = ifc_in32(&fcm->ifc_gcr);
|
|
+ ctrl->saved_gregs->ddr_ccr_low = ifc_in32(&fcm->ddr_ccr_low);
|
|
+ ctrl->saved_gregs->cm_evter_en = ifc_in32(&fcm->cm_evter_en);
|
|
+ }
|
|
+
|
|
+ if (ctrl->saved_rregs) {
|
|
+ /* IFC controller NAND machine registers */
|
|
+ ctrl->saved_rregs->ifc_nand.ncfgr =
|
|
+ ifc_in32(&runtime->ifc_nand.ncfgr);
|
|
+ ctrl->saved_rregs->ifc_nand.nand_fcr0 =
|
|
+ ifc_in32(&runtime->ifc_nand.nand_fcr0);
|
|
+ ctrl->saved_rregs->ifc_nand.nand_fcr1 =
|
|
+ ifc_in32(&runtime->ifc_nand.nand_fcr1);
|
|
+ ctrl->saved_rregs->ifc_nand.row0 =
|
|
+ ifc_in32(&runtime->ifc_nand.row0);
|
|
+ ctrl->saved_rregs->ifc_nand.row1 =
|
|
+ ifc_in32(&runtime->ifc_nand.row1);
|
|
+ ctrl->saved_rregs->ifc_nand.col0 =
|
|
+ ifc_in32(&runtime->ifc_nand.col0);
|
|
+ ctrl->saved_rregs->ifc_nand.col1 =
|
|
+ ifc_in32(&runtime->ifc_nand.col1);
|
|
+ ctrl->saved_rregs->ifc_nand.row2 =
|
|
+ ifc_in32(&runtime->ifc_nand.row2);
|
|
+ ctrl->saved_rregs->ifc_nand.col2 =
|
|
+ ifc_in32(&runtime->ifc_nand.col2);
|
|
+ ctrl->saved_rregs->ifc_nand.row3 =
|
|
+ ifc_in32(&runtime->ifc_nand.row3);
|
|
+ ctrl->saved_rregs->ifc_nand.col3 =
|
|
+ ifc_in32(&runtime->ifc_nand.col3);
|
|
+
|
|
+ ctrl->saved_rregs->ifc_nand.nand_fbcr =
|
|
+ ifc_in32(&runtime->ifc_nand.nand_fbcr);
|
|
+ ctrl->saved_rregs->ifc_nand.nand_fir0 =
|
|
+ ifc_in32(&runtime->ifc_nand.nand_fir0);
|
|
+ ctrl->saved_rregs->ifc_nand.nand_fir1 =
|
|
+ ifc_in32(&runtime->ifc_nand.nand_fir1);
|
|
+ ctrl->saved_rregs->ifc_nand.nand_fir2 =
|
|
+ ifc_in32(&runtime->ifc_nand.nand_fir2);
|
|
+ ctrl->saved_rregs->ifc_nand.nand_csel =
|
|
+ ifc_in32(&runtime->ifc_nand.nand_csel);
|
|
+ ctrl->saved_rregs->ifc_nand.nandseq_strt =
|
|
+ ifc_in32(
|
|
+ &runtime->ifc_nand.nandseq_strt);
|
|
+ ctrl->saved_rregs->ifc_nand.nand_evter_en =
|
|
+ ifc_in32(
|
|
+ &runtime->ifc_nand.nand_evter_en);
|
|
+ ctrl->saved_rregs->ifc_nand.nanndcr =
|
|
+ ifc_in32(&runtime->ifc_nand.nanndcr);
|
|
+ ctrl->saved_rregs->ifc_nand.nand_dll_lowcfg0 =
|
|
+ ifc_in32(
|
|
+ &runtime->ifc_nand.nand_dll_lowcfg0);
|
|
+ ctrl->saved_rregs->ifc_nand.nand_dll_lowcfg1 =
|
|
+ ifc_in32(
|
|
+ &runtime->ifc_nand.nand_dll_lowcfg1);
|
|
+
|
|
+ /* IFC controller NOR machine registers */
|
|
+ ctrl->saved_rregs->ifc_nor.nor_evter_en =
|
|
+ ifc_in32(
|
|
+ &runtime->ifc_nor.nor_evter_en);
|
|
+ ctrl->saved_rregs->ifc_nor.norcr =
|
|
+ ifc_in32(&runtime->ifc_nor.norcr);
|
|
+
|
|
+ /* IFC controller GPCM Machine registers */
|
|
+ ctrl->saved_rregs->ifc_gpcm.gpcm_evter_en =
|
|
+ ifc_in32(
|
|
+ &runtime->ifc_gpcm.gpcm_evter_en);
|
|
+ }
|
|
+
|
|
+/* save the interrupt values */
|
|
+ ctrl->saved_gregs->cm_evter_intr_en = cm_evter_intr_en;
|
|
+ ctrl->saved_rregs->ifc_nand.nand_evter_intr_en = nand_evter_intr_en;
|
|
+ ctrl->saved_rregs->ifc_nor.nor_evter_intr_en = nor_evter_intr_en;
|
|
+ ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en = gpcm_evter_intr_en;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/* restore ifc registers */
|
|
+static int fsl_ifc_resume(struct device *dev)
|
|
+{
|
|
+ struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
|
|
+ struct fsl_ifc_global __iomem *fcm = ctrl->gregs;
|
|
+ struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
|
|
+ struct fsl_ifc_global *savd_gregs = ctrl->saved_gregs;
|
|
+ struct fsl_ifc_runtime *savd_rregs = ctrl->saved_rregs;
|
|
+ uint32_t ver = 0, ncfgr, timeout, ifc_bank, i;
|
|
+
|
|
+/*
|
|
+ * IFC interrupts disabled
|
|
+ */
|
|
+ ifc_out32(0x0, &fcm->cm_evter_intr_en);
|
|
+ ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
|
|
+ ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
|
|
+ ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
|
|
+
|
|
+
|
|
+ if (ctrl->saved_gregs) {
|
|
+ for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
|
|
+ ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr_ext,
|
|
+ &fcm->cspr_cs[ifc_bank].cspr_ext);
|
|
+ ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr,
|
|
+ &fcm->cspr_cs[ifc_bank].cspr);
|
|
+ ifc_out32(savd_gregs->amask_cs[ifc_bank].amask,
|
|
+ &fcm->amask_cs[ifc_bank].amask);
|
|
+ ifc_out32(savd_gregs->csor_cs[ifc_bank].csor_ext,
|
|
+ &fcm->csor_cs[ifc_bank].csor_ext);
|
|
+ ifc_out32(savd_gregs->csor_cs[ifc_bank].csor,
|
|
+ &fcm->csor_cs[ifc_bank].csor);
|
|
+ for (i = 0; i < 4; i++) {
|
|
+ ifc_out32(savd_gregs->ftim_cs[ifc_bank].ftim[i],
|
|
+ &fcm->ftim_cs[ifc_bank].ftim[i]);
|
|
+ }
|
|
+ }
|
|
+ ifc_out32(savd_gregs->rb_map, &fcm->rb_map);
|
|
+ ifc_out32(savd_gregs->wb_map, &fcm->wb_map);
|
|
+ ifc_out32(savd_gregs->ifc_gcr, &fcm->ifc_gcr);
|
|
+ ifc_out32(savd_gregs->ddr_ccr_low, &fcm->ddr_ccr_low);
|
|
+ ifc_out32(savd_gregs->cm_evter_en, &fcm->cm_evter_en);
|
|
+ }
|
|
+
|
|
+ if (ctrl->saved_rregs) {
|
|
+ /* IFC controller NAND machine registers */
|
|
+ ifc_out32(savd_rregs->ifc_nand.ncfgr,
|
|
+ &runtime->ifc_nand.ncfgr);
|
|
+ ifc_out32(savd_rregs->ifc_nand.nand_fcr0,
|
|
+ &runtime->ifc_nand.nand_fcr0);
|
|
+ ifc_out32(savd_rregs->ifc_nand.nand_fcr1,
|
|
+ &runtime->ifc_nand.nand_fcr1);
|
|
+ ifc_out32(savd_rregs->ifc_nand.row0, &runtime->ifc_nand.row0);
|
|
+ ifc_out32(savd_rregs->ifc_nand.row1, &runtime->ifc_nand.row1);
|
|
+ ifc_out32(savd_rregs->ifc_nand.col0, &runtime->ifc_nand.col0);
|
|
+ ifc_out32(savd_rregs->ifc_nand.col1, &runtime->ifc_nand.col1);
|
|
+ ifc_out32(savd_rregs->ifc_nand.row2, &runtime->ifc_nand.row2);
|
|
+ ifc_out32(savd_rregs->ifc_nand.col2, &runtime->ifc_nand.col2);
|
|
+ ifc_out32(savd_rregs->ifc_nand.row3, &runtime->ifc_nand.row3);
|
|
+ ifc_out32(savd_rregs->ifc_nand.col3, &runtime->ifc_nand.col3);
|
|
+ ifc_out32(savd_rregs->ifc_nand.nand_fbcr,
|
|
+ &runtime->ifc_nand.nand_fbcr);
|
|
+ ifc_out32(savd_rregs->ifc_nand.nand_fir0,
|
|
+ &runtime->ifc_nand.nand_fir0);
|
|
+ ifc_out32(savd_rregs->ifc_nand.nand_fir1,
|
|
+ &runtime->ifc_nand.nand_fir1);
|
|
+ ifc_out32(savd_rregs->ifc_nand.nand_fir2,
|
|
+ &runtime->ifc_nand.nand_fir2);
|
|
+ ifc_out32(savd_rregs->ifc_nand.nand_csel,
|
|
+ &runtime->ifc_nand.nand_csel);
|
|
+ ifc_out32(savd_rregs->ifc_nand.nandseq_strt,
|
|
+ &runtime->ifc_nand.nandseq_strt);
|
|
+ ifc_out32(savd_rregs->ifc_nand.nand_evter_en,
|
|
+ &runtime->ifc_nand.nand_evter_en);
|
|
+ ifc_out32(savd_rregs->ifc_nand.nanndcr,
|
|
+ &runtime->ifc_nand.nanndcr);
|
|
+ ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg0,
|
|
+ &runtime->ifc_nand.nand_dll_lowcfg0);
|
|
+ ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg1,
|
|
+ &runtime->ifc_nand.nand_dll_lowcfg1);
|
|
+
|
|
+ /* IFC controller NOR machine registers */
|
|
+ ifc_out32(savd_rregs->ifc_nor.nor_evter_en,
|
|
+ &runtime->ifc_nor.nor_evter_en);
|
|
+ ifc_out32(savd_rregs->ifc_nor.norcr, &runtime->ifc_nor.norcr);
|
|
+
|
|
+ /* IFC controller GPCM Machine registers */
|
|
+ ifc_out32(savd_rregs->ifc_gpcm.gpcm_evter_en,
|
|
+ &runtime->ifc_gpcm.gpcm_evter_en);
|
|
+
|
|
+ /* IFC interrupts enabled */
|
|
+ ifc_out32(ctrl->saved_gregs->cm_evter_intr_en,
|
|
+ &fcm->cm_evter_intr_en);
|
|
+ ifc_out32(ctrl->saved_rregs->ifc_nand.nand_evter_intr_en,
|
|
+ &runtime->ifc_nand.nand_evter_intr_en);
|
|
+ ifc_out32(ctrl->saved_rregs->ifc_nor.nor_evter_intr_en,
|
|
+ &runtime->ifc_nor.nor_evter_intr_en);
|
|
+ ifc_out32(ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en,
|
|
+ &runtime->ifc_gpcm.gpcm_evter_intr_en);
|
|
+
|
|
+ kfree(ctrl->saved_gregs);
|
|
+ kfree(ctrl->saved_rregs);
|
|
+ ctrl->saved_gregs = NULL;
|
|
+ ctrl->saved_rregs = NULL;
|
|
+ }
|
|
+
|
|
+ ver = ifc_in32(&fcm->ifc_rev);
|
|
+ ncfgr = ifc_in32(&runtime->ifc_nand.ncfgr);
|
|
+ if (ver >= FSL_IFC_V1_3_0) {
|
|
+
|
|
+ ifc_out32(ncfgr | IFC_NAND_SRAM_INIT_EN,
|
|
+ &runtime->ifc_nand.ncfgr);
|
|
+ /* wait for SRAM_INIT bit to be clear or timeout */
|
|
+ timeout = 10;
|
|
+ while ((ifc_in32(&runtime->ifc_nand.ncfgr) &
|
|
+ IFC_NAND_SRAM_INIT_EN) && timeout) {
|
|
+ mdelay(IFC_TIMEOUT_MSECS);
|
|
+ timeout--;
|
|
+ }
|
|
+
|
|
+ if (!timeout)
|
|
+ dev_err(ctrl->dev, "Timeout waiting for IFC SRAM INIT");
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+#endif /* CONFIG_PM_SLEEP */
|
|
+
|
|
static const struct of_device_id fsl_ifc_match[] = {
|
|
{
|
|
.compatible = "fsl,ifc",
|
|
@@ -318,10 +576,15 @@ static const struct of_device_id fsl_ifc
|
|
{},
|
|
};
|
|
|
|
+static const struct dev_pm_ops ifc_pm_ops = {
|
|
+ SET_SYSTEM_SLEEP_PM_OPS(fsl_ifc_suspend, fsl_ifc_resume)
|
|
+};
|
|
+
|
|
static struct platform_driver fsl_ifc_ctrl_driver = {
|
|
.driver = {
|
|
.name = "fsl-ifc",
|
|
.of_match_table = fsl_ifc_match,
|
|
+ .pm = &ifc_pm_ops,
|
|
},
|
|
.probe = fsl_ifc_ctrl_probe,
|
|
.remove = fsl_ifc_ctrl_remove,
|
|
--- a/drivers/mtd/maps/physmap_of_core.c
|
|
+++ b/drivers/mtd/maps/physmap_of_core.c
|
|
@@ -20,6 +20,7 @@
|
|
#include <linux/mtd/map.h>
|
|
#include <linux/mtd/partitions.h>
|
|
#include <linux/mtd/concat.h>
|
|
+#include <linux/mtd/cfi_endian.h>
|
|
#include <linux/of.h>
|
|
#include <linux/of_address.h>
|
|
#include <linux/of_platform.h>
|
|
@@ -197,6 +198,9 @@ static int of_flash_probe(struct platfor
|
|
info->list[i].map.bankwidth = be32_to_cpup(width);
|
|
info->list[i].map.device_node = dp;
|
|
|
|
+ if (of_property_read_bool(dp->parent, "big-endian"))
|
|
+ info->list[i].map.swap = CFI_BIG_ENDIAN;
|
|
+
|
|
err = of_flash_probe_gemini(dev, dp, &info->list[i].map);
|
|
if (err)
|
|
goto err_out;
|
|
--- a/include/linux/fsl_ifc.h
|
|
+++ b/include/linux/fsl_ifc.h
|
|
@@ -274,6 +274,8 @@
|
|
*/
|
|
/* Auto Boot Mode */
|
|
#define IFC_NAND_NCFGR_BOOT 0x80000000
|
|
+/* SRAM INIT EN */
|
|
+#define IFC_NAND_SRAM_INIT_EN 0x20000000
|
|
/* Addressing Mode-ROW0+n/COL0 */
|
|
#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
|
|
/* Addressing Mode-ROW0+n/COL0+n */
|
|
@@ -857,6 +859,11 @@ struct fsl_ifc_ctrl {
|
|
u32 nand_stat;
|
|
wait_queue_head_t nand_wait;
|
|
bool little_endian;
|
|
+#ifdef CONFIG_PM_SLEEP
|
|
+ /*save regs when system goes to deep sleep*/
|
|
+ struct fsl_ifc_global *saved_gregs;
|
|
+ struct fsl_ifc_runtime *saved_rregs;
|
|
+#endif
|
|
};
|
|
|
|
extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
|