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96 lines
3.1 KiB
Diff
96 lines
3.1 KiB
Diff
From a00c035c7b82f51716a1a30637b1bd276dee3c5a Mon Sep 17 00:00:00 2001
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From: Biwen Li <biwen.li@nxp.com>
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Date: Wed, 17 Apr 2019 18:58:17 +0800
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Subject: [PATCH] clock: support layerscape
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This is an integrated patch of clock for layerscape
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Signed-off-by: Biwen Li <biwen.li@nxp.com>
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Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
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Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
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Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
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---
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drivers/clk/clk-qoriq.c | 25 ++++++++++++++++++++++---
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drivers/cpufreq/qoriq-cpufreq.c | 1 +
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2 files changed, 23 insertions(+), 3 deletions(-)
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--- a/drivers/clk/clk-qoriq.c
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+++ b/drivers/clk/clk-qoriq.c
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@@ -41,7 +41,7 @@ struct clockgen_pll_div {
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};
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struct clockgen_pll {
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- struct clockgen_pll_div div[4];
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+ struct clockgen_pll_div div[8];
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};
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#define CLKSEL_VALID 1
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@@ -79,7 +79,7 @@ struct clockgen_chipinfo {
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const struct clockgen_muxinfo *cmux_groups[2];
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const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
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void (*init_periph)(struct clockgen *cg);
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- int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */
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+ int cmux_to_group[NUM_CMUX+1]; /* array should be -1 terminated */
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u32 pll_mask; /* 1 << n bit set if PLL n is valid */
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u32 flags; /* CG_xxx */
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};
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@@ -570,6 +570,17 @@ static const struct clockgen_chipinfo ch
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.flags = CG_VER3 | CG_LITTLE_ENDIAN,
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},
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{
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+ .compat = "fsl,lx2160a-clockgen",
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+ .cmux_groups = {
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+ &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
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+ },
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+ .cmux_to_group = {
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+ 0, 0, 0, 0, 1, 1, 1, 1, -1
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+ },
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+ .pll_mask = 0x37,
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+ .flags = CG_VER3 | CG_LITTLE_ENDIAN,
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+ },
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+ {
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.compat = "fsl,p2041-clockgen",
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.guts_compat = "fsl,qoriq-device-config-1.0",
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.init_periph = p2041_init_periph,
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@@ -601,7 +612,7 @@ static const struct clockgen_chipinfo ch
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&p4080_cmux_grp1, &p4080_cmux_grp2
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},
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.cmux_to_group = {
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- 0, 0, 0, 0, 1, 1, 1, 1
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+ 0, 0, 0, 0, 1, 1, 1, 1, -1
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},
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.pll_mask = 0x1f,
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},
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@@ -1127,6 +1138,13 @@ static void __init create_one_pll(struct
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struct clk *clk;
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int ret;
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+ /*
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+ * For platform PLL, there are 8 divider clocks.
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+ * For core PLL, there are 4 divider clocks at most.
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+ */
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+ if (idx != 0 && i >= 4)
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+ break;
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+
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snprintf(pll->div[i].name, sizeof(pll->div[i].name),
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"cg-pll%d-div%d", idx, i + 1);
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@@ -1417,6 +1435,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "
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CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
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CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
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CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
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+CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
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/* Legacy nodes */
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CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
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--- a/drivers/cpufreq/qoriq-cpufreq.c
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+++ b/drivers/cpufreq/qoriq-cpufreq.c
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@@ -320,6 +320,7 @@ static const struct of_device_id node_ma
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{ .compatible = "fsl,ls1046a-clockgen", },
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{ .compatible = "fsl,ls1088a-clockgen", },
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{ .compatible = "fsl,ls2080a-clockgen", },
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+ { .compatible = "fsl,lx2160a-clockgen", },
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{ .compatible = "fsl,p4080-clockgen", },
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{ .compatible = "fsl,qoriq-clockgen-1.0", },
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{ .compatible = "fsl,qoriq-clockgen-2.0", },
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