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199 lines
5.9 KiB
Diff
199 lines
5.9 KiB
Diff
From f147cf49ef39f5e87d5df9ef1fab52683bc75c63 Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Sat, 2 Dec 2017 12:23:09 +0100
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Subject: [PATCH 11/31] pinctrl: gemini: Support drive strength setting
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The Gemini pin controller can set drive strength for a few
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select groups of pins (not individually). Implement this
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for GMAC0 and 1 (ethernet ports), IDE and PCI.
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Cc: devicetree@vger.kernel.org
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Reviewed-by: Rob Herring <robh@kernel.org>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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.../bindings/pinctrl/cortina,gemini-pinctrl.txt | 3 +
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drivers/pinctrl/pinctrl-gemini.c | 81 ++++++++++++++++++++++
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2 files changed, 84 insertions(+)
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--- a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
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+++ b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
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@@ -17,6 +17,9 @@ and generic pin config nodes.
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Supported configurations:
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- skew-delay is supported on the Ethernet pins
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+- drive-strength with 4, 8, 12 or 16 mA as argument is supported for
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+ entire groups on the groups "idegrp", "gmii_gmac0_grp", "gmii_gmac1_grp"
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+ and "pcigrp".
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Example:
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--- a/drivers/pinctrl/pinctrl-gemini.c
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+++ b/drivers/pinctrl/pinctrl-gemini.c
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@@ -67,6 +67,9 @@ struct gemini_pmx {
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* elements in .pins so we can iterate over that array
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* @mask: bits to clear to enable this when doing pin muxing
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* @value: bits to set to enable this when doing pin muxing
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+ * @driving_mask: bitmask for the IO Pad driving register for this
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+ * group, if it supports altering the driving strength of
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+ * its lines.
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*/
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struct gemini_pin_group {
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const char *name;
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@@ -74,12 +77,14 @@ struct gemini_pin_group {
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const unsigned int num_pins;
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u32 mask;
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u32 value;
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+ u32 driving_mask;
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};
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/* Some straight-forward control registers */
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#define GLOBAL_WORD_ID 0x00
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#define GLOBAL_STATUS 0x04
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#define GLOBAL_STATUS_FLPIN BIT(20)
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+#define GLOBAL_IODRIVE 0x10
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#define GLOBAL_GMAC_CTRL_SKEW 0x1c
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#define GLOBAL_GMAC0_DATA_SKEW 0x20
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#define GLOBAL_GMAC1_DATA_SKEW 0x24
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@@ -741,6 +746,7 @@ static const struct gemini_pin_group gem
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/* Conflict with all flash usage */
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.value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
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PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
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+ .driving_mask = GENMASK(21, 20),
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},
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{
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.name = "satagrp",
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@@ -756,6 +762,7 @@ static const struct gemini_pin_group gem
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.name = "gmii_gmac0_grp",
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.pins = gmii_gmac0_3512_pins,
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.num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins),
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+ .driving_mask = GENMASK(17, 16),
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},
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{
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.name = "gmii_gmac1_grp",
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@@ -763,6 +770,7 @@ static const struct gemini_pin_group gem
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.num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins),
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/* Bring out RGMII on the GMAC1 pins */
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.value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
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+ .driving_mask = GENMASK(19, 18),
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},
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{
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.name = "pcigrp",
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@@ -770,6 +778,7 @@ static const struct gemini_pin_group gem
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.num_pins = ARRAY_SIZE(pci_3512_pins),
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/* Conflict only with GPIO2 */
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.value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
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+ .driving_mask = GENMASK(23, 22),
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},
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{
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.name = "lpcgrp",
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@@ -1686,6 +1695,7 @@ static const struct gemini_pin_group gem
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/* Conflict with all flash usage */
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.value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
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PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
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+ .driving_mask = GENMASK(21, 20),
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},
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{
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.name = "satagrp",
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@@ -1701,6 +1711,7 @@ static const struct gemini_pin_group gem
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.name = "gmii_gmac0_grp",
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.pins = gmii_gmac0_3516_pins,
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.num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins),
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+ .driving_mask = GENMASK(17, 16),
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},
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{
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.name = "gmii_gmac1_grp",
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@@ -1708,6 +1719,7 @@ static const struct gemini_pin_group gem
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.num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins),
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/* Bring out RGMII on the GMAC1 pins */
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.value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
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+ .driving_mask = GENMASK(19, 18),
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},
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{
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.name = "pcigrp",
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@@ -1715,6 +1727,7 @@ static const struct gemini_pin_group gem
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.num_pins = ARRAY_SIZE(pci_3516_pins),
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/* Conflict only with GPIO2 */
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.value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
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+ .driving_mask = GENMASK(23, 22),
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},
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{
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.name = "lpcgrp",
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@@ -2423,9 +2436,77 @@ static int gemini_pinconf_set(struct pin
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return ret;
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}
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+static int gemini_pinconf_group_set(struct pinctrl_dev *pctldev,
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+ unsigned selector,
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+ unsigned long *configs,
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+ unsigned num_configs)
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+{
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+ struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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+ const struct gemini_pin_group *grp = NULL;
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+ enum pin_config_param param;
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+ u32 arg;
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+ u32 val;
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+ int i;
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+
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+ if (pmx->is_3512)
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+ grp = &gemini_3512_pin_groups[selector];
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+ if (pmx->is_3516)
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+ grp = &gemini_3516_pin_groups[selector];
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+
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+ /* First figure out if this group supports configs */
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+ if (!grp->driving_mask) {
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+ dev_err(pmx->dev, "pin config group \"%s\" does "
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+ "not support drive strength setting\n",
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+ grp->name);
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+ return -EINVAL;
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+ }
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+
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+ for (i = 0; i < num_configs; i++) {
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+ param = pinconf_to_config_param(configs[i]);
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+ arg = pinconf_to_config_argument(configs[i]);
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+
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+ switch (param) {
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+ case PIN_CONFIG_DRIVE_STRENGTH:
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+ switch (arg) {
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+ case 4:
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+ val = 0;
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+ break;
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+ case 8:
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+ val = 1;
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+ break;
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+ case 12:
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+ val = 2;
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+ break;
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+ case 16:
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+ val = 3;
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+ break;
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+ default:
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+ dev_err(pmx->dev,
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+ "invalid drive strength %d mA\n",
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+ arg);
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+ return -ENOTSUPP;
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+ }
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+ val <<= (ffs(grp->driving_mask) - 1);
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+ regmap_update_bits(pmx->map, GLOBAL_IODRIVE,
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+ grp->driving_mask,
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+ val);
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+ dev_info(pmx->dev,
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+ "set group %s to %d mA drive strength mask %08x val %08x\n",
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+ grp->name, arg, grp->driving_mask, val);
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+ break;
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+ default:
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+ dev_err(pmx->dev, "invalid config param %04x\n", param);
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+ return -ENOTSUPP;
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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static const struct pinconf_ops gemini_pinconf_ops = {
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.pin_config_get = gemini_pinconf_get,
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.pin_config_set = gemini_pinconf_set,
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+ .pin_config_group_set = gemini_pinconf_group_set,
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.is_generic = true,
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};
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