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79 lines
2.2 KiB
Diff
79 lines
2.2 KiB
Diff
From b518bb159032aac33503fd4cf98706dc84cc1266 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Stefan=20Br=C3=BCns?= <stefan.bruens@rwth-aachen.de>
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Date: Thu, 31 Aug 2017 01:06:37 +0200
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Subject: [PATCH] arm64: allwinner: a64: add SPI nodes
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The A64 SPI controllers are register compatible to the h3/h5 SPI
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controllers.
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The A64 has two SPI controllers, each with a single chip select.
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The handles for the DMA channels (23/24 for SPI0/SPI1) are omitted,
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as the A64 DMA support is currently missing.
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Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 41 +++++++++++++++++++
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1 file changed, 41 insertions(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -325,6 +325,16 @@
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drive-strength = <40>;
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};
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+ spi0_pins: spi0 {
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+ pins = "PC0", "PC1", "PC2", "PC3";
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+ function = "spi0";
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+ };
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+
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+ spi1_pins: spi1 {
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+ pins = "PD0", "PD1", "PD2", "PD3";
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+ function = "spi1";
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+ };
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+
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uart0_pins_a: uart0@0 {
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pins = "PB8", "PB9";
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function = "uart0";
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@@ -470,6 +480,37 @@
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};
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};
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+
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+ spi0: spi@01c68000 {
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+ compatible = "allwinner,sun8i-h3-spi";
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+ reg = <0x01c68000 0x1000>;
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+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
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+ clock-names = "ahb", "mod";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi0_pins>;
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+ resets = <&ccu RST_BUS_SPI0>;
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+ status = "disabled";
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+ num-cs = <1>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ spi1: spi@01c69000 {
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+ compatible = "allwinner,sun8i-h3-spi";
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+ reg = <0x01c69000 0x1000>;
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+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
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+ clock-names = "ahb", "mod";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi1_pins>;
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+ resets = <&ccu RST_BUS_SPI1>;
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+ status = "disabled";
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+ num-cs = <1>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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gic: interrupt-controller@1c81000 {
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compatible = "arm,gic-400";
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reg = <0x01c81000 0x1000>,
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