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632 lines
20 KiB
Diff
632 lines
20 KiB
Diff
From 62ac0c4fda3b40a8994f2abfdc52784ced80c83b Mon Sep 17 00:00:00 2001
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From: Biwen Li <biwen.li@nxp.com>
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Date: Wed, 17 Apr 2019 18:58:51 +0800
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Subject: [PATCH] pm: support layerscape
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This is an integrated patch of pm for layerscape
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Signed-off-by: Biwen Li <biwen.li@nxp.com>
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Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
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Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
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Signed-off-by: Li Yang <leoyang.li@nxp.com>
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Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
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Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
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Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
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Signed-off-by: Zhao Chenhui <chenhui.zhao@nxp.com>
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---
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drivers/firmware/psci.c | 16 ++-
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drivers/soc/fsl/rcpm.c | 156 ++++++++++++++++++++
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drivers/soc/fsl/sleep_fsm.c | 279 ++++++++++++++++++++++++++++++++++++
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drivers/soc/fsl/sleep_fsm.h | 130 +++++++++++++++++
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4 files changed, 579 insertions(+), 2 deletions(-)
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create mode 100644 drivers/soc/fsl/rcpm.c
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create mode 100644 drivers/soc/fsl/sleep_fsm.c
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create mode 100644 drivers/soc/fsl/sleep_fsm.h
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--- a/drivers/firmware/psci.c
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+++ b/drivers/firmware/psci.c
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@@ -437,8 +437,18 @@ CPUIDLE_METHOD_OF_DECLARE(psci, "psci",
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static int psci_system_suspend(unsigned long unused)
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{
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- return invoke_psci_fn(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND),
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- __pa_symbol(cpu_resume), 0, 0);
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+ u32 state;
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+ u32 ver = psci_get_version();
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+
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+ if (PSCI_VERSION_MAJOR(ver) >= 1) {
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+ return invoke_psci_fn(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND),
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+ virt_to_phys(cpu_resume), 0, 0);
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+ } else {
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+ state = ( 2 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) |
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+ (1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT);
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+
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+ return psci_cpu_suspend(state, virt_to_phys(cpu_resume));
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+ }
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}
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static int psci_system_suspend_enter(suspend_state_t state)
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@@ -562,6 +572,8 @@ static void __init psci_0_2_set_function
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arm_pm_restart = psci_sys_reset;
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pm_power_off = psci_sys_poweroff;
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+
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+ suspend_set_ops(&psci_suspend_ops);
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}
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/*
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--- /dev/null
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+++ b/drivers/soc/fsl/rcpm.c
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@@ -0,0 +1,156 @@
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+/*
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+ * Run Control and Power Management (RCPM) driver
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+ *
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+ * Copyright 2016 NXP
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ */
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+#define pr_fmt(fmt) "RCPM: %s: " fmt, __func__
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+
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+#include <linux/kernel.h>
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+#include <linux/io.h>
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+#include <linux/of_platform.h>
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+#include <linux/of_address.h>
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+#include <linux/suspend.h>
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+
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+/* RCPM register offset */
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+#define RCPM_IPPDEXPCR0 0x140
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+
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+#define RCPM_WAKEUP_CELL_SIZE 2
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+
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+struct rcpm_config {
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+ int ipp_num;
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+ int ippdexpcr_offset;
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+ u32 ippdexpcr[2];
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+ void *rcpm_reg_base;
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+};
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+
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+static struct rcpm_config *rcpm;
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+
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+static inline void rcpm_reg_write(u32 offset, u32 value)
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+{
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+ iowrite32be(value, rcpm->rcpm_reg_base + offset);
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+}
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+
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+static inline u32 rcpm_reg_read(u32 offset)
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+{
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+ return ioread32be(rcpm->rcpm_reg_base + offset);
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+}
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+
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+static void rcpm_wakeup_fixup(struct device *dev, void *data)
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+{
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+ struct device_node *node = dev ? dev->of_node : NULL;
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+ u32 value[RCPM_WAKEUP_CELL_SIZE];
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+ int ret, i;
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+
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+ if (!dev || !node || !device_may_wakeup(dev))
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+ return;
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+
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+ /*
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+ * Get the values in the "rcpm-wakeup" property.
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+ * Three values are:
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+ * The first is a pointer to the RCPM node.
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+ * The second is the value of the ippdexpcr0 register.
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+ * The third is the value of the ippdexpcr1 register.
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+ */
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+ ret = of_property_read_u32_array(node, "fsl,rcpm-wakeup",
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+ value, RCPM_WAKEUP_CELL_SIZE);
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+ if (ret)
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+ return;
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+
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+ pr_debug("wakeup source: the device %s\n", node->full_name);
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+
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+ for (i = 0; i < rcpm->ipp_num; i++)
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+ rcpm->ippdexpcr[i] |= value[i + 1];
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+}
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+
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+static int rcpm_suspend_prepare(void)
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+{
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+ int i;
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+ u32 val;
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+
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+ BUG_ON(!rcpm);
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+
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+ for (i = 0; i < rcpm->ipp_num; i++)
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+ rcpm->ippdexpcr[i] = 0;
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+
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+ dpm_for_each_dev(NULL, rcpm_wakeup_fixup);
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+
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+ for (i = 0; i < rcpm->ipp_num; i++) {
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+ if (rcpm->ippdexpcr[i]) {
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+ val = rcpm_reg_read(rcpm->ippdexpcr_offset + 4 * i);
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+ rcpm_reg_write(rcpm->ippdexpcr_offset + 4 * i,
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+ val | rcpm->ippdexpcr[i]);
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+ pr_debug("ippdexpcr%d = 0x%x\n", i, rcpm->ippdexpcr[i]);
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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+static int rcpm_suspend_notifier_call(struct notifier_block *bl,
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+ unsigned long state,
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+ void *unused)
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+{
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+ switch (state) {
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+ case PM_SUSPEND_PREPARE:
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+ rcpm_suspend_prepare();
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+ break;
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+ }
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+
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+ return NOTIFY_DONE;
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+}
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+
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+static struct rcpm_config rcpm_default_config = {
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+ .ipp_num = 1,
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+ .ippdexpcr_offset = RCPM_IPPDEXPCR0,
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+};
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+
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+static const struct of_device_id rcpm_matches[] = {
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+ {
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+ .compatible = "fsl,qoriq-rcpm-2.1",
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+ .data = &rcpm_default_config,
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+ },
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+ {}
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+};
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+
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+static struct notifier_block rcpm_suspend_notifier = {
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+ .notifier_call = rcpm_suspend_notifier_call,
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+};
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+
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+static int __init layerscape_rcpm_init(void)
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+{
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+ const struct of_device_id *match;
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+ struct device_node *np;
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+
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+ np = of_find_matching_node_and_match(NULL, rcpm_matches, &match);
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+ if (!np)
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+ return -EINVAL;
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+
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+ if (match->data)
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+ rcpm = (struct rcpm_config *)match->data;
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+ else
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+ return -EINVAL;
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+
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+ rcpm->rcpm_reg_base = of_iomap(np, 0);
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+ of_node_put(np);
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+ if (!rcpm->rcpm_reg_base)
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+ return -ENOMEM;
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+
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+ register_pm_notifier(&rcpm_suspend_notifier);
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+
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+ pr_info("The RCPM driver initialized.\n");
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+
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+ return 0;
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+}
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+
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+subsys_initcall(layerscape_rcpm_init);
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--- /dev/null
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+++ b/drivers/soc/fsl/sleep_fsm.c
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@@ -0,0 +1,279 @@
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+/*
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+ * deep sleep FSM (finite-state machine) configuration
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+ *
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+ * Copyright 2018 NXP
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+ *
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+ * Author: Hongbo Zhang <hongbo.zhang@freescale.com>
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+ * Chenhui Zhao <chenhui.zhao@freescale.com>
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+ *
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+ * Redistribution and use in source and binary forms, with or without
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+ * modification, are permitted provided that the following conditions are met:
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+ * * Redistributions of source code must retain the above copyright
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+ * notice, this list of conditions and the following disclaimer.
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+ * * Redistributions in binary form must reproduce the above copyright
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+ * notice, this list of conditions and the following disclaimer in the
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+ * documentation and/or other materials provided with the distribution.
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+ * * Neither the name of the above-listed copyright holders nor the
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+ * names of any contributors may be used to endorse or promote products
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+ * derived from this software without specific prior written permission.
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+ *
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+ * ALTERNATIVELY, this software may be distributed under the terms of the
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+ * GNU General Public License ("GPL") as published by the Free Software
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+ * Foundation, either version 2 of that License or (at your option) any
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+ * later version.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
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+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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+ * POSSIBILITY OF SUCH DAMAGE.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/io.h>
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+#include <linux/types.h>
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+
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+#include "sleep_fsm.h"
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+/*
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+ * These values are from chip's reference manual. For example,
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+ * the values for T1040 can be found in "8.4.3.8 Programming
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+ * supporting deep sleep mode" of Chapter 8 "Run Control and
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+ * Power Management (RCPM)".
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+ * The default value can be applied to T104x, LS1021.
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+ */
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+struct fsm_reg_vals epu_default_val[] = {
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+ /* EPGCR (Event Processor Global Control Register) */
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+ {EPGCR, 0},
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+ /* EPECR (Event Processor Event Control Registers) */
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+ {EPECR0 + EPECR_STRIDE * 0, 0},
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+ {EPECR0 + EPECR_STRIDE * 1, 0},
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+ {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
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+ {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
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+ {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
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+ {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
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+ {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
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+ {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
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+ {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
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+ {EPECR0 + EPECR_STRIDE * 9, 0x08000084},
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+ {EPECR0 + EPECR_STRIDE * 10, 0x42000084},
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+ {EPECR0 + EPECR_STRIDE * 11, 0x90000084},
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+ {EPECR0 + EPECR_STRIDE * 12, 0x80000084},
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+ {EPECR0 + EPECR_STRIDE * 13, 0x08000084},
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+ {EPECR0 + EPECR_STRIDE * 14, 0x02000084},
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+ {EPECR0 + EPECR_STRIDE * 15, 0x00000004},
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+ /*
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+ * EPEVTCR (Event Processor EVT Pin Control Registers)
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+ * SCU8 triger EVT2, and SCU11 triger EVT9
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+ */
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
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+ /* EPCMPR (Event Processor Counter Compare Registers) */
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+ {EPCMPR0 + EPCMPR_STRIDE * 0, 0},
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+ {EPCMPR0 + EPCMPR_STRIDE * 1, 0},
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+ {EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
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+ {EPCMPR0 + EPCMPR_STRIDE * 3, 0},
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+ {EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
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+ {EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
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+ {EPCMPR0 + EPCMPR_STRIDE * 6, 0},
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+ {EPCMPR0 + EPCMPR_STRIDE * 7, 0},
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+ {EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
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+ {EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
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+ {EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
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+ {EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
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+ {EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
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+ {EPCMPR0 + EPCMPR_STRIDE * 13, 0},
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+ {EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
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+ {EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
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+ /* EPCCR (Event Processor Counter Control Registers) */
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+ {EPCCR0 + EPCCR_STRIDE * 0, 0},
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+ {EPCCR0 + EPCCR_STRIDE * 1, 0},
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+ {EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 3, 0},
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+ {EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 6, 0},
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+ {EPCCR0 + EPCCR_STRIDE * 7, 0},
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+ {EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 13, 0},
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+ {EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
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+ /* EPSMCR (Event Processor SCU Mux Control Registers) */
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+ {EPSMCR0 + EPSMCR_STRIDE * 0, 0},
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+ {EPSMCR0 + EPSMCR_STRIDE * 1, 0},
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+ {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
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+ {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
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+ {EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
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+ {EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
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+ {EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
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+ /* EPACR (Event Processor Action Control Registers) */
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+ {EPACR0 + EPACR_STRIDE * 0, 0},
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+ {EPACR0 + EPACR_STRIDE * 1, 0},
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+ {EPACR0 + EPACR_STRIDE * 2, 0},
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+ {EPACR0 + EPACR_STRIDE * 3, 0x00000080},
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+ {EPACR0 + EPACR_STRIDE * 4, 0},
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+ {EPACR0 + EPACR_STRIDE * 5, 0x00000040},
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+ {EPACR0 + EPACR_STRIDE * 6, 0},
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+ {EPACR0 + EPACR_STRIDE * 7, 0},
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+ {EPACR0 + EPACR_STRIDE * 8, 0},
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+ {EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
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+ {EPACR0 + EPACR_STRIDE * 10, 0x00000020},
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+ {EPACR0 + EPACR_STRIDE * 11, 0},
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+ {EPACR0 + EPACR_STRIDE * 12, 0x00000003},
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+ {EPACR0 + EPACR_STRIDE * 13, 0x06000000},
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+ {EPACR0 + EPACR_STRIDE * 14, 0x04000000},
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+ {EPACR0 + EPACR_STRIDE * 15, 0x02000000},
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+ /* EPIMCR (Event Processor Input Mux Control Registers) */
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+ {EPIMCR0 + EPIMCR_STRIDE * 0, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 1, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 2, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 3, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
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+ {EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
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+ {EPIMCR0 + EPIMCR_STRIDE * 6, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 7, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 8, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 9, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 10, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 11, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
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+ {EPIMCR0 + EPIMCR_STRIDE * 13, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 14, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 15, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
|
|
+ {EPIMCR0 + EPIMCR_STRIDE * 17, 0},
|
|
+ {EPIMCR0 + EPIMCR_STRIDE * 18, 0},
|
|
+ {EPIMCR0 + EPIMCR_STRIDE * 19, 0},
|
|
+ {EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
|
|
+ {EPIMCR0 + EPIMCR_STRIDE * 21, 0},
|
|
+ {EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
|
|
+ {EPIMCR0 + EPIMCR_STRIDE * 23, 0},
|
|
+ {EPIMCR0 + EPIMCR_STRIDE * 24, 0},
|
|
+ {EPIMCR0 + EPIMCR_STRIDE * 25, 0},
|
|
+ {EPIMCR0 + EPIMCR_STRIDE * 26, 0},
|
|
+ {EPIMCR0 + EPIMCR_STRIDE * 27, 0},
|
|
+ {EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
|
|
+ {EPIMCR0 + EPIMCR_STRIDE * 29, 0},
|
|
+ {EPIMCR0 + EPIMCR_STRIDE * 30, 0},
|
|
+ {EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
|
|
+ /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
|
|
+ {EPXTRIGCR, 0x0000FFDF},
|
|
+ /* end */
|
|
+ {FSM_END_FLAG, 0},
|
|
+};
|
|
+
|
|
+struct fsm_reg_vals npc_default_val[] = {
|
|
+ /* NPC triggered Memory-Mapped Access Registers */
|
|
+ {NCR, 0x80000000},
|
|
+ {MCCR1, 0},
|
|
+ {MCSR1, 0},
|
|
+ {MMAR1LO, 0},
|
|
+ {MMAR1HI, 0},
|
|
+ {MMDR1, 0},
|
|
+ {MCSR2, 0},
|
|
+ {MMAR2LO, 0},
|
|
+ {MMAR2HI, 0},
|
|
+ {MMDR2, 0},
|
|
+ {MCSR3, 0x80000000},
|
|
+ {MMAR3LO, 0x000E2130},
|
|
+ {MMAR3HI, 0x00030000},
|
|
+ {MMDR3, 0x00020000},
|
|
+ /* end */
|
|
+ {FSM_END_FLAG, 0},
|
|
+};
|
|
+
|
|
+/**
|
|
+ * fsl_fsm_setup - Configure EPU's FSM registers
|
|
+ * @base: the base address of registers
|
|
+ * @val: Pointer to address-value pairs for FSM registers
|
|
+ */
|
|
+void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val)
|
|
+{
|
|
+ struct fsm_reg_vals *data = val;
|
|
+
|
|
+ WARN_ON(!base || !data);
|
|
+ while (data->offset != FSM_END_FLAG) {
|
|
+ iowrite32be(data->value, base + data->offset);
|
|
+ data++;
|
|
+ }
|
|
+}
|
|
+
|
|
+void fsl_epu_setup_default(void __iomem *epu_base)
|
|
+{
|
|
+ fsl_fsm_setup(epu_base, epu_default_val);
|
|
+}
|
|
+
|
|
+void fsl_npc_setup_default(void __iomem *npc_base)
|
|
+{
|
|
+ fsl_fsm_setup(npc_base, npc_default_val);
|
|
+}
|
|
+
|
|
+void fsl_epu_clean_default(void __iomem *epu_base)
|
|
+{
|
|
+ u32 offset;
|
|
+
|
|
+ /* follow the exact sequence to clear the registers */
|
|
+ /* Clear EPACRn */
|
|
+ for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
|
|
+ iowrite32be(0, epu_base + offset);
|
|
+
|
|
+ /* Clear EPEVTCRn */
|
|
+ for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
|
|
+ iowrite32be(0, epu_base + offset);
|
|
+
|
|
+ /* Clear EPGCR */
|
|
+ iowrite32be(0, epu_base + EPGCR);
|
|
+
|
|
+ /* Clear EPSMCRn */
|
|
+ for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
|
|
+ iowrite32be(0, epu_base + offset);
|
|
+
|
|
+ /* Clear EPCCRn */
|
|
+ for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
|
|
+ iowrite32be(0, epu_base + offset);
|
|
+
|
|
+ /* Clear EPCMPRn */
|
|
+ for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
|
|
+ iowrite32be(0, epu_base + offset);
|
|
+
|
|
+ /* Clear EPCTRn */
|
|
+ for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
|
|
+ iowrite32be(0, epu_base + offset);
|
|
+
|
|
+ /* Clear EPIMCRn */
|
|
+ for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
|
|
+ iowrite32be(0, epu_base + offset);
|
|
+
|
|
+ /* Clear EPXTRIGCRn */
|
|
+ iowrite32be(0, epu_base + EPXTRIGCR);
|
|
+
|
|
+ /* Clear EPECRn */
|
|
+ for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
|
|
+ iowrite32be(0, epu_base + offset);
|
|
+}
|
|
--- /dev/null
|
|
+++ b/drivers/soc/fsl/sleep_fsm.h
|
|
@@ -0,0 +1,130 @@
|
|
+/*
|
|
+ * deep sleep FSM (finite-state machine) configuration
|
|
+ *
|
|
+ * Copyright 2018 NXP
|
|
+ *
|
|
+ * Redistribution and use in source and binary forms, with or without
|
|
+ * modification, are permitted provided that the following conditions are met:
|
|
+ * * Redistributions of source code must retain the above copyright
|
|
+ * notice, this list of conditions and the following disclaimer.
|
|
+ * * Redistributions in binary form must reproduce the above copyright
|
|
+ * notice, this list of conditions and the following disclaimer in the
|
|
+ * documentation and/or other materials provided with the distribution.
|
|
+ * * Neither the name of the above-listed copyright holders nor the
|
|
+ * names of any contributors may be used to endorse or promote products
|
|
+ * derived from this software without specific prior written permission.
|
|
+ *
|
|
+ *
|
|
+ * ALTERNATIVELY, this software may be distributed under the terms of the
|
|
+ * GNU General Public License ("GPL") as published by the Free Software
|
|
+ * Foundation, either version 2 of that License or (at your option) any
|
|
+ * later version.
|
|
+ *
|
|
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
|
|
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
+ * POSSIBILITY OF SUCH DAMAGE.
|
|
+ */
|
|
+
|
|
+#ifndef _FSL_SLEEP_FSM_H
|
|
+#define _FSL_SLEEP_FSM_H
|
|
+
|
|
+#define FSL_STRIDE_4B 4
|
|
+#define FSL_STRIDE_8B 8
|
|
+
|
|
+/* End flag */
|
|
+#define FSM_END_FLAG 0xFFFFFFFFUL
|
|
+
|
|
+/* Block offsets */
|
|
+#define RCPM_BLOCK_OFFSET 0x00022000
|
|
+#define EPU_BLOCK_OFFSET 0x00000000
|
|
+#define NPC_BLOCK_OFFSET 0x00001000
|
|
+
|
|
+/* EPGCR (Event Processor Global Control Register) */
|
|
+#define EPGCR 0x000
|
|
+
|
|
+/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
|
|
+#define EPEVTCR0 0x050
|
|
+#define EPEVTCR9 0x074
|
|
+#define EPEVTCR_STRIDE FSL_STRIDE_4B
|
|
+
|
|
+/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
|
|
+#define EPXTRIGCR 0x090
|
|
+
|
|
+/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
|
|
+#define EPIMCR0 0x100
|
|
+#define EPIMCR31 0x17C
|
|
+#define EPIMCR_STRIDE FSL_STRIDE_4B
|
|
+
|
|
+/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
|
|
+#define EPSMCR0 0x200
|
|
+#define EPSMCR15 0x278
|
|
+#define EPSMCR_STRIDE FSL_STRIDE_8B
|
|
+
|
|
+/* EPECR0-15 (Event Processor Event Control Registers) */
|
|
+#define EPECR0 0x300
|
|
+#define EPECR15 0x33C
|
|
+#define EPECR_STRIDE FSL_STRIDE_4B
|
|
+
|
|
+/* EPACR0-15 (Event Processor Action Control Registers) */
|
|
+#define EPACR0 0x400
|
|
+#define EPACR15 0x43C
|
|
+#define EPACR_STRIDE FSL_STRIDE_4B
|
|
+
|
|
+/* EPCCRi0-15 (Event Processor Counter Control Registers) */
|
|
+#define EPCCR0 0x800
|
|
+#define EPCCR15 0x83C
|
|
+#define EPCCR31 0x87C
|
|
+#define EPCCR_STRIDE FSL_STRIDE_4B
|
|
+
|
|
+/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
|
|
+#define EPCMPR0 0x900
|
|
+#define EPCMPR15 0x93C
|
|
+#define EPCMPR31 0x97C
|
|
+#define EPCMPR_STRIDE FSL_STRIDE_4B
|
|
+
|
|
+/* EPCTR0-31 (Event Processor Counter Register) */
|
|
+#define EPCTR0 0xA00
|
|
+#define EPCTR31 0xA7C
|
|
+#define EPCTR_STRIDE FSL_STRIDE_4B
|
|
+
|
|
+/* NPC triggered Memory-Mapped Access Registers */
|
|
+#define NCR 0x000
|
|
+#define MCCR1 0x0CC
|
|
+#define MCSR1 0x0D0
|
|
+#define MMAR1LO 0x0D4
|
|
+#define MMAR1HI 0x0D8
|
|
+#define MMDR1 0x0DC
|
|
+#define MCSR2 0x0E0
|
|
+#define MMAR2LO 0x0E4
|
|
+#define MMAR2HI 0x0E8
|
|
+#define MMDR2 0x0EC
|
|
+#define MCSR3 0x0F0
|
|
+#define MMAR3LO 0x0F4
|
|
+#define MMAR3HI 0x0F8
|
|
+#define MMDR3 0x0FC
|
|
+
|
|
+/* RCPM Core State Action Control Register 0 */
|
|
+#define CSTTACR0 0xB00
|
|
+
|
|
+/* RCPM Core Group 1 Configuration Register 0 */
|
|
+#define CG1CR0 0x31C
|
|
+
|
|
+struct fsm_reg_vals {
|
|
+ u32 offset;
|
|
+ u32 value;
|
|
+};
|
|
+
|
|
+void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val);
|
|
+void fsl_epu_setup_default(void __iomem *epu_base);
|
|
+void fsl_npc_setup_default(void __iomem *npc_base);
|
|
+void fsl_epu_clean_default(void __iomem *epu_base);
|
|
+
|
|
+#endif /* _FSL_SLEEP_FSM_H */
|